One of the toughest obstacles faced by designers of embedded real-time systems comes from the same new technology that fuels this fast-moving industry. Our insatiable demand for more powerful, smaller, and less expensive processors and peripherals has driven the wizards of silicon to produce generation after generation of increasingly faster devices.

However, system infrastructures for connecting these devices to each other and to real world peripherals have not kept pace with the data transfer demands of the new devices. In trying to close this I/O gap, Pentek has developed the VIM (Velocity Interface Mezzanine) architecture, a new royalty-free, open-system, high-performance mezzanine bus delivering extremely high-speed data transfers suitable for a variety of processors and board formats.

Real-time system performance often suffers more from bottlenecks in interconnections than from device speeds. For details on data rates for new processors, see New Processors Drive the Data Rates.

Several techniques have evolved to address this problem in open-architecture, board level embedded systems, but each has its drawbacks. The role of the backplane in these systems, for example, is shifting from its traditional task of providing a data flow channel between boards to that of handling control, status and initialization tasks.

Even though some newer high-speed backplane technologies are emerging, the concept of arbitrating for a common bus shared across multiple boards proves limiting in the more demanding applications. As a result, alternative techniques for moving data across the backplane, like RACEway, have grown in acceptance, although the cost of implementation and packaging can be significant.

One of the most traditional methods of delivering dedicated, high-speed interconnects between boards is the mezzanine or daughter board. Over the years, dozens of mezzanine architectures have evolved.

Most were inspired by the specific needs of a particular product or manufacturer and, therefore, remained obscure, company proprietary designs. However, after years of use, refinement, definition and numerous committee meetings, a few mezzanine designs have evolved into true industry standards. Unfortunately, the most popular standard mezzanine busses still fall far short of meeting the needs of recently introduced DSP and RISC processors. For details on differing mezzanine design standards, see Comparing Mezzanine Designs.

Pentek ran up against this shortfall when trying to meet the high-speed I/O demands of the Texas Instruments TSM320C6201 on our quad processor VMEbus board, the Model 4290. Pentek needed a mezzanine structure that could provide a private parallel data path to each processor supporting up to 100MHz transfer rates for 32-bit words.

We also wanted to accommodate high speed serial interconnects to speeds of 100Mbits/sec, especially well suited for the many digital telecom interfaces and other serial peripherals. Front panel access for the many different types of signal interfaces and the wide variety of associated connectors was also essential. In addition, provisions for shielding of critical analog and RF circuitry were required for supporting wideband data converters and software radio functions.

Since no existing mezzanine standard could meet our requirements, we embarked on a new mezzanine design. In order to help ensure acceptance from a broad industry base, Pentek created the mezzanine architecture to be non-proprietary, royalty-free and completely independent of any one processor or manufacturer.

New Processors Drive the Data Rates | Comparing Mezzanine Designs

Overview of VIM

While defining the new mezzanine, nicknamed VIM, for Velocity Interface Mezzanine, we focused on two parallel, often conflicting goals. The immediate goal was to meet the performance needs of our boards, with tight development and delivery schedules.

The second goal was to make decisions in implementation which would allow VIM to work not only with next generation TI processors, but also with the newest DSP and RISC devices from other manufacturers as well, fully consistent with our open standard mandate. Our design is shown in Figure 1.

Figure 1: The essential elements of the VIM electrical bus consist of three interfaces—the streaming parallel bus, the serial interface and the control/status interface.

VIM Streaming Parallel Bus

To decouple the processor and the streaming parallel interface, the VIM interface uses synchronous, bi-directional FIFO memories, or synch Bi-FIFOs. Synch Bi-FIFOs provide consistent, industry-standard timing and have the added benefit of buffering input and output data to the processor, taking optimal advantage of the efficient block transfers.

DMA controllers supporting the processor can easily utilize the software configurable interrupt flags of the Bi-FIFOs for automatic data transfers between the processor memory and peripheral devices, thus freeing the processor core to concentrate on more worthy tasks. Any idiosyncratic timing provisions between the processor and the Bi-FIFO are transparent to the mezzanine interface. Since many processors already support synchronous DRAM interfaces, synchronous FIFOs are typically not difficult to handle.

There are numerous benefits to using Bi-FIFOs for the parallel interface. With two independent ports, the Bi-FIFO supports wide disparities between mezzanine data rates and processor data rates. The mezzanine port can be clocked at any rate up to its maximum of 100MHz, supporting both fast and slow peripherals as well as clocking which is either periodic, non-periodic, or "bursty". Without the Bi-FIFO, the processor would have to try to be ready to take or deliver data at just the right time, imposing a serious constraint on processing tasks.

On the processor side, the Bi-FIFO can be loaded or unloaded whenever it is convenient, usually at the end of a processing loop when block transfers of data make the most sense. Prudent real-time signal processing design techniques require that the processor task execution time for a block of data is (at least slightly) shorter than the time it takes to collect that block. In this way, the processor finishes all of its "homework" and waits (perhaps briefly) for the next data block to become ready. Bi-FIFO buffering embodies the ideal implementation of this approach.

Bi-FIFOs also allow slower processors to handle very high-speed streams. A good example is the new RACE++ standard from Mercury, which specifies 32-bit words transferred at 66.66MHz. The 100MHz Bi-FIFO VIM mezzanine port easily absorbs inbound RACEway packets and allows a slower processor to subsequently unload the data at a slower rate. Likewise, the slower processor can leisurely fill the Bi-FIFO with an outgoing packet and then initiate the RACEway interface to deliver the packet at the full rate from the VIM mezzanine port.

Table 1 summarizes the signals associated with the streaming parallel bus. All signals are single ended and compliant with TTL levels. Note that the in/out signal direction is relative to the mezzanine module.

Table 1: Streaming Bi-FIFO VIM Signals
Signal	Lines	Direction	Description
Data Bits	32	In/Out	Bi-directional data lines
FIFO Clock	1	Out	Clock for mezzanine FIFO port
FIFO Chip Select	1	Out	Enables the FIFO clock for reads & writes
FIFO Direction	1	Out	Determines the FIFO read/write model
FIFO Input Flags	3	In	Full, almost full, and almost empty
FIFO Output Flags	3	In	Empty, almost empty, and almost full
FIFO Reset	1	Out	Clears contents of FIFO
Processor Interrupt	1	In	Interrupt signal from processor
Mailbox Interrupt	1	In	Interrupt from FIFO mailbox
Mailbox Select	1	Out	Enables reads & writes to FIFO mailbox

In addition to connecting to the VIM mezzanine module, the VIM Bi-FIFO flags are available to serve as interrupt inputs to the baseboard processor. The VIM module may also interrupt the baseboard processor by writing to one of two special mailbox registers contained within the Bi-FIFO.

VIM Serial Ports

The VIM serial interface supports two full duplex channels, each with two data lines, three clock lines and two framing signals. These seven signals provide an extremely flexible and configurable interface to many different types of serial devices. Table 2 shows each of the lines.

Table 2: Serial Port VIM Signals
Signal	Lines	Direction	Description
Receive Data	2	Out	One line for each of two serial ports
Receive Clock	2	In/Out	''
Receive Frame Sync	2	Out	''
Transmit Data	2	In	''
Transmit Clock	2	In/Out	''
Transmit Frame Sync	2	Out	''
External Clock	2	Out	''

The receive and transmit clock lines can be configured under software to support peripherals which must either receive or supply clocks. An external clock signal may be applied to replace the processor's serial clock timing reference.

Many of the new processors feature integral serial ports, often with sophisticated framing and TDM hardware conveniently linked to DMA controller signals. This nicely supports serial streams from digital telecom interfaces like E1/T1 and matches the processing functions of the telecom-oriented DSPs like the 'C6203 which can handle a full T1 span of V.90 modems.

VIM Random Access Control/Status Interface

Controlling the interfaces and circuitry on the mezzanine module is accommodated with the VIM random access control/status bus, which closely resembles a generic microprocessor interface. This allows registers and other programmable resources on the module to be mapped into a conveniently located read/write address region of the processor memory space.

Signals present on this portion of the VIM interface are shown below in Table 3. The names of most of the lines are self-explanatory.

Table 3: Random Access Control / Status VIM Signals
Signal	Lines	Direction	Description
Data Bus	32	In/Out	Bi-directional data bus (buffered to processor)
Address Bus	16	In	Address lines (subset of processor address
Output Enable	1	In	Enables the module to drive data bus
Read Strobe	1	In	Read control signal
Write Enable	1	In	Write control signal
Ready Output	1	Out	Data transfer complete acknowledge
Reset	1	In	Resets or initializes the module
Clock Input	1	In	Processor related clock
Interrupt Output	1	Out	Interrupt to the processor
Module Present Output	1	Out	Indicates that a module is installed

Power Supply

Power supply lines from the motherboard include +5 VDC and ±12 VDC for powering the module. The number of pins for each supply and the maximum current for the module is shown in Table 4. The recommended total maximum power dissipation is 15W.

Table 4: Power Supply VIM Interface
Signal	# Pins	Total Currents
+5V	20	3 Amps
+12V	1	1 Amp
-12V	1	1 Amp
GND	23	--

Mechanical Aspects of VIM

Pin and socket style connectors were selected for the baseboard/module interconnect. These compact 160- pin, four-row connectors occupy a minimal board footprint of 2.1 x 0.25 inches and feature both male and female in surface mount versions, conserving valuable inner-layer printed circuit board real estate.

Figure 2: In the first implementation, the Model 4290 Quad 'C6201 DSP 6U processor board, the VIM connectors were arranged in a single line parallel to the front panel. This arrangement gives each processor its own private VIM interface and allows module designs that span one, two, or all four processor connection sites.

A fifth connector, of the same style as the four VIM processor connectors, is installed near the rear of the board just in front of the P2 backplane connector. This 200- pin interconnect includes a shared global bus as well as the 64 user-defined pins of the VME P2 connector to support mezzanine board connections to RACEway. This fifth connector is not part of the VIM specification, and can be specific to the needs of a particular baseboard.

Figure 3: Figure 3 shows the 4290 as viewed from the back plane connectors, with the four VIM processor connectors the global bus and P2 connector identified. Note that the front panel is segmented, allowing two blank front panel sections to be removed to make provisions for the front panels of VIM mezzanine modules.

VIM Module Formats

So far, several different mezzanine module form factors have been defined for the quad 'C6x DSP boards using the VIM specification. These meet the various needs of a wide range of applications, but the first and most popular is the VIM-2 format shown in Figure 4.

Figure 4: So far, several different mezzanine module form factors have been defined for the quad 'C6x DSP boards using the VIM specification. These meet the various needs of a wide range of applications, but the VIM-2 format shown here is the first and most popular.

Figure 5: A front panel becomes part of the front panel of the DSP board, nesting in the same slot as the DSP board. It attaches to two of the four processor nodes and allows two completely independent interfaces to each DSP through interface circuitry to front panel I/O functions.

Figure 6: The final assembly with two VIM-2 modules attached to the baseboard. Note that the complete assembly occupies only one VMEbus slot.

Figures 7 and 8: The VIM-2 format shown in Figure 7 (left) allows two different types of VIM interfaces to be combined on the same DSP board, perhaps supporting an input function with one module and an output function with the other. Other VIM mezzanine form factors include the VIM-4, which provides connectivity from all front panel connectors to all four DSPs as shown in Figure 8 (right).

Figures 9 and 10: Two more VIM module formats take advantage of the fifth global bus and P2 connector. The VIM-4R format shown in Figure 9 (left) supports a RACEway or VSB interface to all four processor nodes.

The VIM-2R in Figure 10 combines the benefits of a RACEway interface for two of the processors with the ability to install a VIM-2 module for other I/O functions. This configuration can take advantage of the inter-processor pipeline FIFOs found on high-performance 'C6x boards to connect high speed front panel interfaces through a powerful DSP engine, and then out to RACEway devices for additional processing or storage.

Sample VIM-based Systems

Currently available VIM module functions include FPDP, RACEway, digital receivers, parallel TTL I/O, serial I/O, multi-channel A/D, and high-speed A/D converters. Each module takes advantage of the high-speed parallel or serial interfaces provided by VIM, whichever is most appropriate for the module circuitry.

Figure 11: An example system shows the Model 4290 Quad 'C6201 DSP processor VIM baseboard, equipped with two VIM-2 modules. The entire system shown occupies only a single 6U VMEbus slot.

The first module is the Model 6216 Dual Channel Wideband Digital Receiver, which digitizes two HF or IF band analog signals, performs a digital frequency translation and delivers a baseband signal with Nyquist bandwidths from 1 to 32.5MHz. Two 32-bit, complex digital wideband signals are fed directly across the VIM interface into the synchronous Bi-FIFOs on the processor baseboard and subsequently into two 'C6201s (A and B) for processing. The combined data rate for both channels is 260MB/sec.

Interprocessor Bi-FIFOs (identical to the VIM mezzanine Bi-FIFOs) allow processors A and B to transfer data at a combined rate of up to 800MB/sec to processors C and D for more signal processing. Processors C and D deliver output data to the second module, a Model 6226 Dual FPDP (front panel data port) VIM-2 module. Dual FPDP ports on the front panel support two 160MB/sec channels to other high-speed system components using an industry standard interface.

VIM Specification Status

The VIM specification has been evolving for slightly more than a year now. It has been used successfully by several customers of Pentek's 'C6x boards to design custom high-performance interfaces for complex or proprietary functions not available as standard board products. The benefit of being able to take advantage of the most advanced quad 'C6x processor architecture and all of the supporting hardware and software tools available for it, offers a significant reduction in development effort and time to market for unique or unusual applications.

Following extremely favorable initial acceptance by customers, Pentek has adopted VIM as its high-performance mezzanine of choice as designs migrate to new processors and new module functions. Pentek intends to promote VIM as a non-proprietary, open industry standard, incorporating third-party refinements as the specification matures.

The VIM specification is available for viewing or downloading at www.pentek.com/vimspec after you register to gain access.