| Table 3: Seventeen signals of the link layer to physical layer interface
|
|
|
|
|
| Signal Name
|
Source
|
Description
|
| LReq
|
Link request
|
Link request—used to initiate a request to
send a packet, as well as a request to read
directly from a PHY register.
|
| SClk
|
Physical layer
|
49.152MHz clock used to synchronize data
readout. (The frequency may change
depending on data rates with 1394b.)
|
| Data[0:7]
|
Either
|
Data—higher transfer speeds use an
increasing number of bits:
100Mbps —D[0:1]
200Mbps —D[0:3]
400Mbps —D[0:7]
Note that the width of this data bus may
expand to 16 bits with 1394b.
|
| Ctl[0:1]
|
Either
|
Control interface—defines what state the
interface is in.
|
| LPS
|
Link Layer
|
Link power status—indicates that the link
layer controller is powered.
|
| Link On
|
Physical layer
|
Indicates that the physical layer has been
powered on.
|
| Direct
|
Neither
|
Indicates that no isolation barrier exists.
|
| Backplane
|
Physical layer
|
High if physical layer is a backplane
implementation.
|
| Clk25
|
Neither
|
Indicates that SClk is only 24.576MHz;
valid in a backplane implementation only.
|
