Microchip has itnroduced its next generation eight-bit RISC architecture. Promising software and hardware design reusability, the PIC18CXXX allows existing PICmicro eight-bit RISC MCU users to migrate their designs to higher integration while maintaining their code and hardware investment via socket compatibility with existing printed-circuit boards. The ’18CXXX architecture offers up to two million bytes of program memory address space, a C compiler-friendly development environment, and 10 MIPS performance at 40MHz.

Technical specifications

The PIC18CXXX is upward compatible from the ’12C6XXX, the ’16CXXX, and the ’17CXXX cores. It features:

• Linear address space . The on-chip memory addressing scheme can accommodate up to two million bytes of program memory and 4K of data memory

• Additional instructions . The ’18CXXX combines the bit-manipulation instructions and byte-manipulation instructions from existing mid- and high-end PICmicro CPUs, including the 8 x 8 single-cycle hardware multiply and table read/write. It’s a 16-bit instruction and an eight-bit data ALU architecture

• Designed for C compiler efficiency . The inclusion of linear program memory removes all paging-related overhead. Data memory is linear, as well. The available 128 bytes of “access RAM” are suitable for global variable allocation. Three 12-bit-wide data pointer registers with pre-increment, post-increment, post-decrement, and offset-addressing modes make it possible to implement the run-time parameter stack efficiently. The top of the hardware PC stack is readable and writable, making it possible to manage the stack entirely in software

• Modular emulation tool . A combination of master-slave emulator chips emulate the actual part. The master chip emulates the CPU and the program memory access, while the slave chip emulates all the peripherals

The PICmicro OTP microcontrollers can be programmed in-circuit after being placed in a circuit board.

PIC18CXXX devices

The PIC18CXXX architecture is initially being implemented in four MCU devices. They feature 16K to 32K of on-chip EPROM (OTP) program memory and 512 bytes to 1,536 bytes of data SRAM. These devices provide various feature sets of 10-bit analog-to-digital converters; capture, compare, and pulse-width modulation; and I ² C, SPI, and USART communications capability.

The ’18C242 and ’18C442 feature 8,192 x 16 bits of OTP program memory and 512 bytes of user RAM. The ’18C252 and ’18C452 offer 16,384 x 16 bits of OTP program memory and 1,536 bytes of user RAM. The ’18C242 and ’18C252 are available in 28-pin PDIP and SOIC packages, and the ’18C442 and ’18C452 are available in 40- and 44-pin PDIP, PLCC, and TQFP packages.

Development systems

The PIC18Cxxx is supported by the MPLAB-C18 C compiler. A 30-day full-featured demo of MPLAB-C18 can be downloaded from the company’s Web site.

The MPLAB-ICE 2000 universal in-circuit emulator provides real-time emulation for the PIC18CXXX. The system features the MPLAB integrated development environment. Interchange-able processor modules and device adapters allow the emulator system to be easily configured to emulate different processors.

Price and availability

Pricing in 10,000-unit quantities is $5.98 each for the ’18C242, $6.79 each for the ’18C442, $6.61 each for the ’18C252, and $7.41 each for the ’18C452. Samples will be available in August, with volume shipments scheduled for the third quarter. The MPLAB-C18 C Compiler will be available in August for $495. The MPLAB-ICE 2000 Universal ICE is available now starting at $1,995.

Microchip Technology

Chandler, AZ

(602) 786-7200

www.microchip.com

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