Pixel Magic -- a video enhancement system implemented on embedded platforms -- improves video quality with high efficiency and low cost for a wide variety of portable digital devices.
Architecture
The architecture of Pixel Magic Video Engine is depicted in
Figure 3.
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Figure 3: Architecture of Pixel Magic Video Engine
The system has been implemented on several embedded architectures such as TI's DSP and ARM. When running on the TMS320C64x DSP core, it delivers D1 (720x480) resolution video at 30 fps and will soon be able to handle HD content using as little as 900MHz. When running on the ARM926EJ-S core, it can provide enhanced video to quarter VGA resolution (QVGA) video using less than 120 MHz.
In an example where Pixel Magic Video Engine is used to enhance video on the display device, the decoded video data (usually in YUV format, i.e., pixels are represented as a combination of lumas and chromas) is sent into an algorithm core, where it is processed by a variety of proprietary enhancement modules.
Enhanced video data is then transferred into an output buffer where the data is converted into a suitable display format. Finally, the data is displayed on the screen.
Input buffer
The Input buffer uses special memory allocation techniques to re-arrange video data into a structure that can be quickly loaded by algorithm modules, so the time for data movement is significantly reduced. It then sends video data to an algorithm core via the bus.
The input buffer also provides an API (Application Program Interface) that is capable of receiving raw video data in several commonly used formats.
Next: Algorithm core, output buffer
