When will an ASIC project cost a billion bucks? You might be surprised.
Mojy Chian, Richard Cliff, and Jeff Watt have an interesting article at
EDN.COM entitled "
Achieving First-Time Success at 40 nm,"
in which they describe how Altera is migrating their FPGA line to the
40 nm process node.
The sidebar gives the percentage of ASIC design starts at various
geometries, starting from bigger than 0.5 micron in 2002 to projections
of 22 nm in 2011. At that point the engineering cost on a bleeding-edge
ASIC project will exceed $100 million, a rather horrifying number.
Projections are always fun, and it's entertaining though dangerous
to extrapolate from both current data and other people's projections.
So I fit curves, selected somewhat arbitrarily based on "looks like a
good match," to the article's data:

The pink line is the process geometry, and the extrapolation looks
like a pretty good match to historical data from the last half-dozen
years. Between 2002 and 2008 the effect of Moore's Law is simply
stunning. No other industry has achieved any similar sort of
improvement in anything over such a short period.
After 2014 it's hard to extract much from the graph, but around 2018
this curve predicts features will be about an angstrom across, roughly
the size of a single atom. That's absurd, of course, though today gate
oxides on some parts are just an astonishing few atoms thick.
But clearly something has to happen before we get to that node. It
won't be quantum computing because even the optimists figure that's
years off. Maybe Moore's Law will finally sputter
out. Wags have
predicted its demise for years, only to be proven wrong every time.
Around the same time engineering costs would, if these trends
persist, reach about a cool billion bucks. As Senator Everett Dirksen
reputedly said, "A billion here, a billion there, pretty soon you're
talking real money." Few products will tolerate $10E9 NRE costs.
I carried the projection out further. In about 50 years the cost of
just one ASIC project will exceed the United State's current GDP.
It'll be a hell of a product, though.
Those these numbers are "projectio ad absurdum." But they do
show an approaching moment of inflection where some significant change
in high-end semiconductors will be required, a change that's
revolutionary rather than additional incremental improvements. Some
scaling hard limit surely exists, be it the Planck length or, more
likely, at the atomic level. And the atomic level just isn't that many
years away.
Jack G. Ganssle is a lecturer and consultant on embedded
development issues. He conducts seminars on embedded systems and helps
companies with their embedded challenges. Contact him at jack@ganssle.com. His website is www.ganssle.com.