During the past four years, the NAND flash memory architecture has become the predominant memory type applied in consumer electronics because of its data storage and retrieval capabilities.

For the previous 15 years, designers used NOR flash memory for code applications in practically every type of embedded system. It was designed for code execution: the so-called, execute-in-place (XiP) model; however, as products have evolved, especially mobile consumer devices, NOR has been tasked with storing limited amounts of data as well, though it is handicapped by slow write speeds and high cost. The NAND architecture was developed specifically with data applications in mind. NAND flash inherently enables fast write speeds and the construction of much denser nonvolatile memory at a much lower cost per bit than NOR flash.

But with new application requirements in many embedded systems, especially consumer electronics, there is a growing need for converged architectures combining the capabilities of both.

From Voice- to Data-centric
Direct XiP capability, an SRAM-like interface, read bandwidth of up to 108 MB/s and random accessibility made NOR flash ubiquitous in voice-centric handsets. The multiplexed interface of NAND flash memories was not built into the controllers or processors of the time, which limited NAND flash to dedicated applications.

When considered as data-centric memory, NAND provides several distinct advantages over NOR as a storage medium, including far faster write speed, much lower cost per bit, and increased reliability. NAND can be written at 17 MB/s, about 100 times faster than can a comparable MLC (multi-level-cell) NOR device. NAND is roughly 40 percent less expensive in cost per bit than NOR at similar densities and NAND can be scaled to 4 Gb in a single device, whereas NOR has not exceeded 1Gb.

Finally, from a reliability standpoint, NAND implementations have built-in error correction protocols and bad-block management similar to hard disk drives. NOR, as a directly addressable memory, has no provisions to handle errors. A bad bit in NAND can be handled transparently to a user but a bad bit in NOR can result in a costly system crash or time-consuming file corruption.

New Combinations
Now, voice-centric cellular handsets typically use a NOR flash memory for code and an SRAM or pseudo SRAM for dynamic data processing. The combination works for storage requirements of less than 16 MB, with operating systems that perform limited functions.

As more functions have been added to handsets (cameras, MP3 audio) and such sophisticated operating systems as Symbian, Linux and Windows Mobile, have been employed, the need for data storage has increased so much that a third memory – a NAND flash device – became necessary to hold data.

Moreover, the amount of volatile memory and bandwidth requirements grew so much that SRAM or PSRAM has been replaced by a mobile DRAM that has up to 10 times the bandwidth and much lower cost-per-bit than SRAM or PSRAM. Consequently, the OS has increasingly taken advantage of that bandwidth and instead of being executed from the NOR device, moves its code-base into DRAM on power-up in a store-and-download (SnD) approach.

In that memory model, the NOR device is used primarily for booting at power up; the lower-cost NAND device is used for storage; and the DRAM is used for executing data applications, for buffering and for other high-speed tasks.

Some designers questioned why so much budget should be devoted to an XiP-capable NOR device when it is used only to boot a system. Chipset companies have responded and added bootable NAND controllers to their products, for the first time enabling a NOR-less system with the NAND device handling both the code and data functions required by the handset.

Demand Paging
The memory model of a pure NAND + DRAM play is increasingly applied. In that model, the code base is transferred from NAND to DRAM on power-up and executes from DRAM while in use. However, some designers wonder why the entire code base must be transferred to DRAM when merely portions that are needed at any given moment could be transferred thereby reducing the size of the DRAM required. Given that challenge, a new model is gaining favor: demand paging.

Demand paging has been used in PCs for many years to allow the hard drive to supplement the amount of installed DRAM, as needed. Assuming that the desired pages of code can be summoned quickly when needed, the entire demand paging process can be transparent to the end user, resulting in a substantial reduction in the DRAM required and a significant savings in materials.

Using a demand paging approach, the key to performance efficiency is how quickly a page can be read from the NAND memory into DRAM. The ideal flash solution would have the read bandwidth of NOR flash (108 MB/s) and the write speed and low cost of a NAND device. To meet that objective, converged flash/SRAM fusion architectures such as OneNAND from Samsung have begun to emerge.

NAND-NOR-SRAM Fusion
One of a number of new converged flash device architectures being proposed, OneNAND has a NAND flash array at its core but adds logic and SRAM buffers to map the NAND flash to a NOR interface. The device can be read at NOR speeds and can be written at NAND speeds, while maintaining NAND’s low-cost structure.

In addition, error correction logic is built into the device and it even has an SRAM-mapped boot RAM so that systems without a NAND interface can seamlessly connect to such devices. As a NAND-NOR-SRAM fusion memory it is designed to satisfy the needs of a demand paging environment in next-generation handsets.

The core NAND architecture is transparent to the application processor, which can issue a command to load a page from the NAND array to the SRAM buffer, then read that page via the NOR interface. This process happens automatically on power-up for the first 1kB of code, which becomes available for booting via the 1kB BootRAM memory mapped to the fusion architecture’s base address. By doing this, it can be used as the unified flash solution for any processor with an SRAM interface.

Software is key
In addition to its efficient SnD architecture, NAND Flash uses three software elements that ease the implementation and improve the performance of consumer and mobile electronics.

First, a low-level driver tells the system how to connect with the memory. Second, a flash translation layer serves to extend the life of the flash memory through a process called wear-leveling and also handles all command conversions.

Flash-memory cells typically have a practical limit of about 100,000 writes and wear-leveling aids any application that may exceed that limit. Suppose a designer has a file that must be updated every second.

To avoid data writing problems, the wear-leveling software changes the correlation between logical and physical mapping for each write command, thereby extending the life of the flash so much that cell wear-out is no concern. The mapping, with negligible processor overhead, moves frequently updated information around the memory device to different locations.

The flash translation layer also must convert what are essentially hard-disk-drive commands (issued by the file system) to flash commands. In a disk drive, new data simply overwrites old but flash cells require erasure, which typically occurs in blocks of 128 kB.

Finally, the file-system sits on top of this memory stack, logically mapping files to sectors and providing director services. Two types of file-systems exist: traditional FAT file systems that have only a master allocation table (Windows FAT32, for example) and transactional file systems that keep a log of each transaction to prevent an operation from being corrupted if power is lost.

For designers to transition from voice-centric NOR flash memory to higher-performing NAND flash memory, integration software support is imperative. Handsets account for roughly half the NOR flash market and such embedded applications as hand-held industrial scanners, various security devices, remote sensors, GPS systems and even network servers account for another quarter or more of the market.

Lower-volume applications
When millions of consumer products are produced from a single design, custom software is a relatively inexpensive. But software development is a prohibitive cost for most embedded products, where products generally number in the hundreds of thousands of units or less. Such products employ many operating systems and widely varied hardware, therefore software to support a NAND flash design must be versatile as well as inexpensive.

Accordingly, now available is prepackaged flash software support for the OneNAND fusion flash architecture to work smoothly in embedded applications, the result of a cooperative venture between the software manufacturer Datalight and Samsung. This will hasten the NOR-replacement time line for certain applications, particularly those that require 128 Mb to 1 Gb of memory and a separate file system, with frequent data writes.

NOR flash memory has become less practical to use than NAND flash memory in new generations of mobile products in which multimedia functions are the driver, though NOR will continue to be use in voice-centric handsets. However, a sharp rise in demand for NAND calls for greater care in planning by consumer-electronics OEMs, embedded-systems designers and industrial-device designers as applications grow more complex, use faster processors and have a greater need for memory.

Don Barnetson is associate director of flash memory marketing at Samsung Semiconductor, Inc.