The incessant demand for faster high speed serial link interconnects has given rise to a plethora of serial link technologies, many of which promise to increase the speed to 12.5Gbps. To achieve the lowest bit error rate margin for a particular channel environment requires careful consideration of a number of critical issues.

This article will discuss the different issues associated with legacy and next-generation backplanes. For instance, manufacturing variations and environmental conditions have a significant impact on the performance of high-speed backplane systems.

System designers must consider these variations and ensure that the systems perform with acceptable bit-error rates under the specified conditions.

The criteria upon which the selection of an appropriate signaling scheme should be made are discussed. In addition, cutting edge serial link technologies, collectively known as Advanced Backplane (ABP), will be discussed. Among the technologies encompassed in ABP are Smart Decision Feedback Equalizer (SmartDFE) and Automatic Adaptation.

Predictions of continued economic recovery and expansion of various data networks drive a resurgence of new design activity at networking equipment vendors.

The result is bandwidth increase that demands dramatic improvements in serial link performance. Developing capable high-performance serial link solutions that comprehensively satisfy the stringent backplane requirements for these platforms poses substantial challenges.

System designers must overcome a host of manufacturing variations, temperature and humidity variations, all of which have significant impact on the performance of high-speed backplane systems. System designers must consider these variations and ensure that the systems perform with acceptable bit-error rates (BERs) under the specified conditions.

The backplane channel is typically composed of ten independent components: the die, package, and module of the line and switch cards, the two backplane connectors, the backplane module and the AC-coupling capacitor, as identified in Figure 1, below.

High speed serial link problems
Serial links can have various trace lengths and via stub-lengths on the line, switch and backplane PCB modules and chip packages. The links also go through numerous connector pair combinations which result in various impedance and crosstalk profiles.

Typically, the serializer-deserializer (SerDes) circuits used in high-speed serial links are designed to minimize the impact of channel impairments. At higher data rate, variations in manufacturing process, humidity and temperature must also be taken into account.

Two of the more destructive channel impairments encountered in high-speed backplanes are inter-symbol interference (ISI) and reflections. Effectively minimizing the effect of these impairments is the predominant challenge of the system designer, designer, especially as speeds attain and exceed 10 Gbps.

One of the significant effects of channel dispersion is the 'spreading' of adjacent symbols which causes successive bits to overlap, resulting in bit error. To understand ISI, consider the backplane transfer function in frequency domain. In the frequency domain, the backplane channel behaves like a low-pass filter, attenuating high-frequency components while leaving the low-frequency largely unaffected (Figure 2, below).

The most common approach to cancel ISI is to introduce Inverse Frequency Equalization (IFE), which behaves like a high-pass filter. This form of transmit equalization (pre-emphasis and de-emphasis) is a straight forward and effective way to minimize the effect of ISI. In pre-emphasis, high-frequency components are amplified and de-emphasis attenuates the low-frequency components relative to the signaling Nyquist frequency, thus flattening the overall system response and removing ISI.

In the time domain, single-bit response of the channel demonstrates the destructive effect of ISI. Figure 3 below illustrates a simple 1-0-1 pattern transmitted down a lossy channel to a receiver. The resulting error induced by 'pre-cursor' ISI (the blue waveform) added with 'post-cursor' ISI (the green waveform), produces a voltage for the '0' bit significantly above the 0/1 voltage threshold.

Reflections due to impedance mismatches occur at a number of different points in the channel. As previously shown in Figure 1, the channel is the complete path from one die to the other die through packages soldered to line cards that plug into the backplane.

The signal has to traverse a number of traces to get from source to destination, each represented by potentially different impedance characteristics.

Impedance discontinuities
The short vertical traces, or vias, that connect the components of the system are another source of reflections. These vias connect the package to the line card, and from the line card into the connector and the backplane.

The connectors themselves frequently have internal impedance discontinuities, or can have discontinuities when combined with line-card and backplane vias in a real system. Time domain reflection (TDR) analysis illustrates such impedance discontinuities (Figure 4, below).

The most effective way to minimize the effect of reflections in the channel is through careful design, manufacture and integration of the various passive components in the channel. However, another form of equalization called Decision Feedback Equalization (DFE) can deal effectively with loss and dispersion ISI while minimizing configuration-dependent reflections as well. This technique uses both transmit and receive equalizers to boost or attenuate each bit, based on prior knowledge of the channel characteristics.

One of the key advantages of this equalization approach is that it can compensate for late-term reflections. Perhaps the most important advantage of DFE, however, is that it can be programmed to continuously adapt to changes in the channel brought about by environmental fluctuations.

Since dispersion varies as a function of many properties in backplanes, flexibility in the transmit equalizer in tap settings is highly desirable. Similarly, as the receive equalizer is predominantly used for minimizing reflections, flexibility in tap assignments and weights is critical for dealing with the varying reflections present in different high-performance backplane configurations.

In a typical backplane environment with substantial channel-to-channel variations, there is no simple set of coefficients that will work for all channels. By using adaptation, one can simultaneously determine the optimum solution for each of the equalization coefficients.

In the classical manual solutions, coefficients are determined by exhaustively predefining the various links SerDes will run over. In a typical 14-line card chassis, there are many line cards, switch cards, control cards, and chassis revision combinations.

Manual tuning of the equalization coefficients could consume many man-months of design and test engineering resources. In the 'continuous' (or adaptive) equalization method, coefficients continuously and automatically adapt during live data transmission.

Thermal and humidity variations are the two most common effects requiring continuous adaptation in the backplane. They in turn cause changes in the channel transfer function. Humidity variations combined with temperature variations of 60° C or more can cause variations of up to 10dB in channel performance at 3GHz.

Lacking the ability to continuously adapt the equalization to compensate for these variations, the manual method will likely fail to achieve and maintain acceptable BER.

Traditional equalization constraints
Traditional equalization is peak-constrained. As shown in Figure 2(b) earlier, the 'gain' in equalizer is actually attenuation of as much as -10dB at low frequencies. In channels made of traditional dielectric materials, a.k.a. FR-4, received signal is severely attenuated to begin with. Applying traditional equalization, which attenuate low frequencies further, is at times impractical.

Against this problem, recently introduced is a new approach known as Smart Decision Feedback Equalizer (SmartDFE). Instead of changing the signal, this new DFE approach is designed to anticipate the affects of ISI and attenuation and intelligently subtract the negative impact.

To effectively compensate the pre-cursor ISI induced by the previously received bit, one must remove the effect of the previously received bit before the subsequent bit arrives. This is very hard to accomplish in high speed links, because bits arrive so quickly that the latency of the receiver circuits can be much longer than the bits themselves when designing within reasonable power constraints. In order to get around this limitation, we developed a SmartDFE receiver with loop unrolling (Figure 5, below).

In the SmartDFE receiver, two samples are made simultaneously, and the correct bit is selected based on the previous bit decision. In other words, the SmartDFE receiver uses a form of speculative sampling and decision making that allows sampling of the next bit before the previous bit is resolved.

In addition to the standard data slicers and edge samplers to facilitate 2x over-sampled clock and data recovery, the receiver has one extra sampler used for monitoring the link performance. This adaptive sampler has variable timing and voltage references and in addition to monitoring performance during link operation it also provides the information necessary for the adaptive equalization and link configuration algorithms.

To achieve first-tap DFE without excessive power consumption one tap of immediate feedback equalization in the receiver was added using loop unrolling to avoid the bottleneck in the latency of the feedback loop. Since we cannot run the feedback loop fast enough, we unroll it once and make two decisions each cycle.

One comparator decides the input as if the previous output was a 1, and the other comparator decides the input as if the previous bit was a 0. Once we know the previous bit, we select the correct comparator output, as shown in Figure 5, above.

Using two samplers
Instead of just one data sampler for signaling, the receiver now has two samplers that are offset by ± , anticipating the impact of the trailing (post-cursor) ISI tap , from a previously sent symbol of value of ±1. By using two receivers, one conditioned to assume an error of + and the other " , when we determine the actual value of the previous bit we can select the output of the correct receiver. This concept is very similar to that of carry-select adders.

To demonstrate how this works, consider the bit series of 0-1-1-0 as depicted in Figure 6, below. The first bit (1) arrives, including its post-cursor error, causing a + error shift on the next bit (0). By simultaneously sampling at two separate points in the voltage domain, one at + and the other at - , and having determined that the initial bit was a (1), the output of the + receiver is selected for the second bit.

Similarly, post-cursor spreading of the second bit causes a - error shift on the third bit which, when the value of the second bit has been determined, results in the selection of the     - receiver for the third bit. The use of two samplers with ± offsets makes this technique possible.

There are numerous benefits to employing an adaptive receive equalizer in conjunction with this approach. The frequency response of different channels in the same backplane can vary greatly for many reasons: variations in board and device manufacturing, different loss slopes due to different lengths, notches due to discontinuities that the signal encounters in the connectors and vias as wires change routing layers, to name a few.

To ensure that a given link architecture will work well on every channel in the backplane, you must be prepared to custom fit the equalization to each. However, a large number of links in a backplane puts a huge overhead on centralized link control. From this perspective, a more desirable solution is to design a self-contained link that can adapt itself to the channel.

Moreover, each channel varies slowly over time due to changes in temperature and humidity, with channel loss fluctuating as much as 10dB at 3GHz. These significant changes require the equalizer to be re-adjusted, rather than merely setting and forgetting it upon initial installation. Thus, an adaptive equalization methodology ensures optimal performance for every channel at all times and in all conditions.

Another benefit " one that translates to reduced implementation costs " is the inherent advantage of this approach over the exclusive use of linear transmit equalization. Receiver feedback equalization merely subtracts the error from the input with no signal attenuation. Conversely, since the output swing of the transmitter is limited by a peak power constraint, a transmit equalizer must attenuate the low frequency components of the signal to create a flat response for the channel.

Thus, using this methodology in conjunction with transmit equalization results in as much as a 40 percent higher voltage margin than a fully transmit-equalized signal (Figure 7, above).

In short, this can enable the system designer to employ less expensive dielectric materials in the PCB and still maintain sufficient voltage margin to ensure optimal performance.

Leo Wong runs networking and storage product planning and market development at Rambus. 

<>References:
[1] V. Stojanovic et al., "Adaptive Equalization and Data Recovery in a Dual-Mode PAM2/4 Serial Link Transceiver"

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