Power management solutions for today's portable applications processors are becoming highly integrated. Total power consumption, standby and deep-sleep current consumption affect battery size, bill of materials (BOM) cost and product acceptance.

System designers must consider many variations of power supplies when designing portable devices such as smart phones or PDAs. As they get more power-hungry, smart phones require highly integrated power-management solutions to achieve the overall design goal of maximum battery life in the smallest PCB area possible.

Today's applications processors require separate power domains for the core, I/Os, memory and peripherals. The LP3971, for instance, is a power management unit (PMU) designed to meet all of these requirements using three high efficiency buck converters and six low dropout (LDO) regulators.

Applications processors require multiple power-supply voltages, which can be optimized as demanded by the core power manager and system architecture. LP3971 meets a wide range of system requirements with I2C-controlled output voltages, factory-configurable power-on sequencing and default output voltages.

This article focuses on powering a microprocessor's low voltage rail in a PDA/smarphone application using devices such as the LP3971 which combine buck converter and LDO functions.

When designing a system, the architect must balance such requirements as cost, PCB area, component size, talk time, standby time, battery capacity and schedule. The microprocessor RAM requires a 1.5V supply with a maximum current of 400mA. Let's start with the simplest, lowest-cost solution - an LDO regulator connected directly to the Li-ion battery (Figure 1, below).

Figure 1: The simplest, lowest-cost solution for an applications processor is an LDO regulator connected directly to the Li-ion battery.

The battery voltage will start at 4.2V and decrease to 3.2V, where the system enters into deep sleep until the battery is recharged or replaced. Figure 2 below shows a typical Li-Ion battery discharge cycle.

For the configuration shown in Figure 1, the efficiency of LDO 5 will be: LDO percent efficiency = [(V_out * I_out) / V_in * (I_out + I_q)] * 100. For this and all other examples in this article, I_q is removed because it is very low (40 microAmps) compared with I_out (400 milliamps).

The efficiency equation then becomes:

Percent efficiency = [(V_out)/(V_in)] * 100.

For V_in = 4.2V and V_out = 1.5V, the LDO efficiency is 1.5/4.2 = 36 percent. Total power is P_t = 4.2 * 0.400 = 1.70W.

Figure 2.A typical Li-ion battery discharge cycle.

All power that is not delivered to the output load is dissipated as heat within the LDO. Dissipated power is estimated as:

Dissipated power (P_d) = (V_in - V_out) * I_out = (4.2 - 1.5) * 0.400 = 1.1W, dissipated as heat.

We have just calculated the maximum continuous power (P_t). RAM will not operate at this level for very long. If we look at a 10 percent duty cycle, the average power consumption will be:

P_t = 0.10 * 1.7 = 0.17W.

The amount of time the RAM operates at Imax depends on the application, power-management firmware and OS. In Figure 2, the battery voltage does not stay at 4.2V for long. At a nominal battery voltage of 3.6V, Vout is still at 1.5V; the LDO efficiency is 42 percent.

Figure 3. The input of LDO 5 is connected to the output of buck 3, which is set at 1.8V to power memory.

If the system requires lower power consumption and the configuration in Figure 1 is not acceptable, consider the solution shown in Figure 3, above where the input of LDO 5 is connected to the output of buck 3, which is set at 1.8V to power memory. For the configuration shown in Figure 3, when the input of LDO 5 is connected to a 1.8V rail, the efficiency is calculated as:

Efficiency = V_out/ V_in = (1.5V/1.8V) * 100 = 83 percent.

Dissipated power is estimated as:

P_d = (V_in - V_out) * I_out = (1.8 - 1.5) * 0.400 = 0.12W, which will be dissipated as heat.

The LDO 5 efficiency is 83 percent. Note that if we were to use a switching supply instead of LDO 5, the efficiency could be as low as 85 percent - an improvement of just 2 percent for this block. However, overall efficiency depends on the type of converter that is used.

Using the efficiency curves from the LP3671 buck converter datasheet (Figure 4, below), the overall system loss due to this double conversion DC/DC + LDO will be 78 percent. An LDO is the lowest-cost, smallest-size and lowest-noise solution.

Figure 4. Using these efficiency curves, the overall system loss due to this double conversion DC/DC + LDO will be 78 percent.

Adding another DC/DC converter to power the RAM will increase the PCB area due to the addition of a very large external inductor (3mm x 3mm) by 10 mm² and increase the overall noise of your system. If a 1.8V supply is not available, any buck converter voltage rail that is lower than V_batt can be used. The lower the LDO input voltage, the higher the efficiency - as long as the input voltage is above V_out + V_dropout.

There is no reason to worry when using an LDO to power low-voltage microprocessors. Ask yourself: "Do I really want to use an extra buck converter and inductor to improve system efficiency by just a few percent?"

Using a buck converter to power the low-voltage rails will increase the size of the power management IC, add another 3mm x 3mm inducto, and increase the BOM cost and PCB area. In contrast, an LDO is inexpensive, small and easy to use. It is also the lowest noise solution that can be optimized for your application.

Ken Marasco is a System Architect at National Semiconductor Corp.