Verifying and debugging memory-system designs that use DDR2 SDRAM is challenging because of the signal speeds, complex signal-timing sequences, and the many signals that need to be acquired and analyzed.

A logic analyzer with memory support gives the designer a powerful tool to verify and debug memory systems. The logic analyzer captures all the memory signals and shows the operation of the DDR2 SDRAM (Data Double Rate Synchronous Dynamic Random Access Memory) signals in a waveform window and a listing window. These two windows give designers insight into the memory system's operation, enabling them to verify and debug it.

The memory support:

• Configures the logic-analyzer channel assignments.
• Defines channel groups.
• Provides DDR2 SDRAM-specific state clocking.
• Defines command symbols used in triggering and bus forms.
• Decodes the mode-register bit fields.
• Decodes SDRAM commands into mnemonics.
• Displays read and write data in the listing window.

We start the memory analysis by using the logic analyzer's waveform window, which is similar to an oscilloscope's display, but displays large numbers of signal traces. When acquiring the signals of a 1-Gbyte, 240-pin unbuffered DIMM using DDR2 SDRAM, the logic analyzer acquires and analyzes over 90 signal traces (see the Table 1).

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Sampling resolution
Figure 1 shows the waveform window of a DDR2 SDRAM's address, clock, commands, data, and data strobes. The vertical ticks in the top row of the waveform represent the logic analyzer's sampling resolution. The ticks are 125 ps apart, and the signals are sampled at 8 GHz. These marks show when the logic analyzer sampled the DDR2 SDRAM signals. It's important to understand that a high sampling rate provides finer and more detailed signal acquisition and analysis, versus using a lower sampling rate.

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The logic analyzer's sampling resolution also defines the sampling uncertainty of the logic analyzer. In this example (Figure 1), the uncertainty in the measurement of the signal edges is 125 ps before the vertical sampling tick marks in the waveform window.

Individual strobe signals
For clarity, the logic analyzer organizes the signals into groups. Figure 1 shows single-channel waveforms for the memory-command signals DDRCK0, S1#, S0#, RAS#, CAS#, and WE#. Signal groups are used for address, data, and data strobes. The address group contains the 14 address signals and three bank address signals. The DIMM 64 bits of data are divided into most significant 32 bits of RdA_DatHi and the least significant 32 bits of RdA_DatLo. The strobes group contains eight strobes because there are eight DDR2 SDRAMs on this DIMM.

The state of the signals in bus form is represented by hexadecimal numbers. At cursor one, the center vertical dash line, the address state is 1B020, the most significant 32 data bits are 88888877, the least significant 32 bits are 77888877, and the strobes are 00. All the groups in Figure 1 have a plus sign (+) before the group name, meaning that signals are shown in bus form and can be expanded into individual waveforms. By clicking on the +, the individual signals are visible below the bus form with the eight strobes, as in Figure 2.

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The bus form's cross pattern shows that there are signal transitions at that location in the waveforms. Expanding the bus form to the individual signals shows the details of each signal transition. The strobes' transition zone is 375 ps, which is measured by using the logic analyzer's user-defined markers. In Figure 2, strobes 0 and 2 transition first and strobe 4 transitions last. The same analysis can also be done on the other bus-form groups.