Read/write analysis
Figure 3 shows two separate waveform windows stacked one above each other. The top (write) window shows the timing of two 64-bit write-data words. The bottom (read) window shows the timing of two 64-bit read-data words. Notice the differences between write and read data-valid windows with respect to the cursors at the rising edge of the DDR2 SDRAM clock. Different data-valid windows for write and read data are common for DDR2 SDRAM. Write data is centered within the data strobes and approximately center-aligned with the clock edges. Read data is edge-aligned with the data strobes and approximately edge-aligned with the clock edges.

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Also in Figure 3, the top write-window"command-group values are represented in hex, while in the bottom read window, the group values are represented in symbols. Using symbols reduces the effort needed to understand the timing waveforms.

Capturing the write and read in state acquisition requires configuring eight logic-analyzer sample-point positions for the eight data-valid windows that have their hexadecimal values underlined. State acquisition uses the rising edge of DDRCK0 with regard to the eight sample-point positions, to acquire all possible write and read data-valid windows in the DDR2 SDRAM clock cycle. After the logic analyzer stops its acquisition, the memory support decodes the commands and determines the correct sampled data to be used.

To effectively work between the waveform window and the listing window, cursors one and two are locked between the windows. Locking cursors provides an easy way to correlate the data between the waveform window and the listing window.

The listing window
In Figure 4, the listing window is the state-acquisition display of the DDR2 SDRAM signals that the logic analyzer acquired. The logic analyzer uses the listing window to show the state-acquisition data and to decode the command signals into mnemonics. The listing window has columns with logic analyzer's sample number, address, command mnemonics, 32-bit high and low data, and logic analyzer's time stamp of the sample. You can modify the listing window to show other data such as data mask, check bits, and bank address.

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The listing window provides a higher logical view of the signals than the waveform window. One sample in state acquisition represents one complete DDR2 clock cycle. One sample in high-resolution timing represents 125 ps. In time duration, one state-acquisition sample equals 30 high-resolution timing samples.

DDR2 SDRAM burst their data in groups of four or eight. The burst length is configured by the memory controller in the mode register. In Figure 4, the burst lengths are four for the read and write commands.

A typical read-data sequence starts with an activate command, opening a row in a specific bank. Next, one or more reads are completed on columns in the opened row. Finally, the row is closed by a precharge command. A typical write sequence starts with an activate command opening a row in a specific bank. Next, one or more writes are completed on columns in the opened row. Again, the row is closed by a precharge command. By using a listing window you can quickly check the SDRAM for correct operation such as commands sequences, commands timing, burst length, and correct data.

Time-stamp considerations
A perfect DDR2-533 SDRAM clock period is 3.752 ns. For this example, the DDR2-533 SDRAM clock period is 3.744 ns. The logic analyzer used has a high-resolution timing of 125 ps and therefore the logic analyzer's time-stamp resolution is 125 ps. Hence, the time stamp between the state acquisitions is usually 3.750 ns. Sometimes it'll be 125 ps less (3.625 ns) or greater (3.875 ns). The time-stamp reference is from the previous displayed sample. You can select the time-stamp reference to a previous displayed sample, system trigger, cursor one, cursor two, or have it show absolute time.

Selective clocking stores DDR2 SDRAM data when commands are present and for 13 clock cycles after column-address assertion, resulting in more bus-cycle activity and fewer idle cycles being stored in the logic analyzer's acquisition memory.