All or part of the listing-window data can be exported to a file. The data can be exported as an ASCII text file, binary file, or Tektronix TLA Data Exchange format. You can modify the exported data and load it into simulation programs or automatic-test-equipment systems.
Mode registers
The DDR2 SDRAM mode registers are programmed by the memory controller during the memory system's power-up configuration phase. The MRS command programs the mode registers using the address and bank-address signals. The bank addresses select the mode register and the address signals configure the mode-register bit fields.
By using the logic analyzer's conditional storage, you can choose to store only mode-register commands and, therefore, more efficiently use the logic-analyzer memory. Figure 5 shows the last of the mode-register commands that configured the DDR2 SDRAM. The listing-window's address column contains the bank's 3-bit address as most significant bits and 14-bit address as the least significant bits. The bank-address bits determine which mode register is configured with data on the 14-bit addresses. The logic analyzer decodes which mode register is being accessed and decodes the data on the 14-bit address signals into bit-field descriptions.
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The mode register was programmed with both a latency and burst length of four. You can see this in Figure 4, where for the sample 154 read commands, the first word of read data on the SDRAM data bus is four cycles later (at sample 158). The two words contained on sample 158 occur because DDR2 transfers two data words per clock cycle and one logic analyzer's state acquisition on one DDR2 clock cycle. Notice that at sample 158, while the SDRAM transmits the two data words, the memory controller has also sent another read command to the SDRAM. Sample 154 read command (four data words) is in samples 158 and 159 because, as already mentioned, the burst length is four. The read command at sample 156 has its data on the bus starting four cycles later at sample 160 and completes its burst length of four with sample 161.
These back-to-back reads from sample 158 to 165 fully utilize the DDR2 SDRAM data bus at its full data rate. The read commands can't be sent in adjacent command cycles because every read requires two clock cycles to output its data. As a result, the fastest that the memory controller can send read commands is every other DDR2 clock cycle. If the burst length was eight, there would be three DDR2 clock cycles between each back-to-back read command.
DDR2 SDRAM write latency is the read latency minus one. Therefore, the write command at sample 138 has its data on the bus starting three DDR2 clock cycles later at sample 141 and completes its burst length of four with sample 142. The write command at sample 140 has its data on the bus starting three DDR2 clock cycles later at sample 143 and completes its burst length of four with sample 144.
Be aware that the DDR2 SDRAM's additive latency in the first extended mode register will add cycles between the read and write commands and their data. In this example, the additive latency is zero and no additional DDR2 clock cycles are added between the read and write commands and their data.
The logic analyzer is the tool of choice to verify and debug memory systems. The logic analyzer captures all memory signals and shows the operation of DDR2 SDRAMs in a high-level state listing window, as well as in a detailed timing waveform window that lets designers identify faults in the DDR2 SDRAM digital signals.
David Haworth is a logic-analyzer memory-application specialist at Tektronix. He was one of the founders of the VXIplug&play Systems Alliance and SCPI Consortium. Haworth can be reached at dave.a.haworth@exgate.tek.com.
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