A standard interface combines with an on-chip controller to handle the wear-leveling and write/erase timing, as well as the memory management functions of your NAND memory.

Nonvolatile memory has many functions in a processor-based system, but one of the most critical is providing the initial firmware that the processor must use in its system initialization (boot) process. Both NAND flash, with its interface challenges, and NOR flash, with its relatively low density, are unsatisfactory for use as single, nonvolatile, bootable system memory. Managed NAND offers a third alternative, once the challenge of making it bootable has been solved.

Portable devices, such as personal media players (PMPs) and portable navigation devices (PNDs), have at least two requirements for nonvolatile semiconductor memory. One need, common to all processor-based systems, is nonvolatile program storage. For many systems, only the power-up initialization or boot programs need to reside in semiconductor memory. PMPs and PNDs, however, typically need their entire software package, including applications and operating systems, in semiconductor memory. This requires at least moderate memory capacity, from tens to hundreds of megabytes. In all cases, the memory must be compatible with the processor's boot process.

Second, these systems must have user data storage. In the case of PMPs, the data would be music and video files. For PNDs, the data include maps, location markers, and movement histories. What these data types all have in common is large size. User storage capacity of hundreds of megabytes to gigabytes is quickly becoming a consumer expectation. Unlike program storage, the data memory can be block-oriented rather than pure random access.

The nonvolatile memory of choice in today's devices is flash, which stores its data as a charge imposed on a floating gate in a CMOS transistor, as shown in Figure 1. The presence of the charge determines the transistor's state, hence the memory cell's data value. Because the gate is floating, with no direct connection to any other circuits, any charge placed on the gate remains indefinitely unless deliberately removed.

To charge or discharge the floating gate, the memory cell must impose a high-voltage signal on the transistor's other gate. Electrons then tunnel to or from the floating gate. This high voltage stresses the insulators and crystalline structures around the floating gate and can eventually damage those structures, rendering the memory cell useless. This wear-out mechanism is common to all forms of flash memory.

Another attribute common to all flash memory is the need to erase a cell before writing to it. Because a cell's state may not be known before attempting to store data into it, the control logic on flash devices first puts the cell into a known (erased) state before configuring it with data. Thus, every time a cell is written to, it suffers some wear-out damage.

Two distinct flash memory architectures have arisen: NOR and NAND. NOR, as shown in Figure 2, has an SRAM-like structure. Each individual bit in the memory connects to the word and bit lines of the device's internal addressing circuitry and the output level is normally high. If a memory cell has been programmed, activating it with the proper word line causes it to pull the bit line low, as with wired-NOR logic.

The individual bit connections give NOR flash a relatively simple RAM-like external interface and high read speed. Erasing or writing to the memory, especially in large blocks, takes extra time, however. Each bit in the block must be individually erased to prepare the block for writing, which can add up to a significant amount of time if the block is large.