When you need to measure the differential voltage at a particular point in a circuit, you are not yet likely to find a "Vdiff" function in your SPICE simulator. You are going to have to define this by hand. If you want to plot the common-mode signal, again you must define it yourself. Of course now that it is printed in a book, the programmers will put it in.

Differential signaling enables very high data rates on circuit boards. But traditional techniques for controlling skew and for distributing clocks run out of gas at these speeds. The answer is often embedded clocks and de-skewing inside the silicon.

A typical embedded clock is implemented by encoding the data in such a way that there is a guaranteed minimum transition rate, or number of signal edges per unit of time. Then, a phase-locked loop can be used with this data to recover the clock.

In the days of parallel buses, the skew between the data lines and between the data and clock were a major concern. Skew is the difference in flight-time for the various individual traces.

Even if the lines were all carefully laid out to be exactly the same length, variations in the dielectric constant in the board material caused skew. As bus rates increased, skew became a factor limiting the maximum usable bus rate. The reason was the way data was strobed into the receiver.

The parallel data would arrive at each of the bit latches and when all had settled and were stable, the clock or strobe would trigger all the latches simultaneously to capture the data. If some were earlier and some later, all would have to wait for that last bit to be ready. The range of arrival times for the individual bits became a major limiting factor on how fast the bus could ultimately run.

In high-speed serial systems, de-skewing is done electrically rather than mechanically. De-skewing can be done by mechanisms such as measuring the time-offset of each input and selecting a particular clock phase that best matches it. It is fairly easy to generate a range of clock phases to facilitate this.

This method in turn necessitates a circuit training plan in which the relationship between clock and data can be measured. As the arrival phases of the individual signals are identified, the optimal clock phase for each can be locked in. So, the issue of skew between differential pairs that are not within an individual pair has passed into the realm of non-issue.

Because perfect components, components with no time delay and no parasitics, come naturally to SPICE, it is very easy to set up a differential driver—two outputs with complementary signals. Of course, there are a few standard warnings. As in any modeling task, be sure to include appropriate parasitics. For example, the tool can quite easily implement a behavioral driver that has no capacitance to ground.

In the real world, such a thing will never exist. As is typical of driver models, the important things to get right are the output voltage or current swing, the rise and fall times, the impedance, and the capacitance. In addition, differential drivers have both common-mode and differential impedance, and these can be independent of each other. The point is, take care to get them right.