When you need to measure the differential voltage at a particular point in a circuit, you are not yet likely to find a "Vdiff" function in your SPICE simulator. You are going to have to define this by hand. If you want to plot the common-mode signal, again you must define it yourself. Of course now that it is printed in a book, the programmers will put it in.

Differential signaling enables very high data rates on circuit boards. But traditional techniques for controlling skew and for distributing clocks run out of gas at these speeds. The answer is often embedded clocks and de-skewing inside the silicon.

A typical embedded clock is implemented by encoding the data in such a way that there is a guaranteed minimum transition rate, or number of signal edges per unit of time. Then, a phase-locked loop can be used with this data to recover the clock.

In the days of parallel buses, the skew between the data lines and between the data and clock were a major concern. Skew is the difference in flight-time for the various individual traces.

Even if the lines were all carefully laid out to be exactly the same length, variations in the dielectric constant in the board material caused skew. As bus rates increased, skew became a factor limiting the maximum usable bus rate. The reason was the way data was strobed into the receiver.

The parallel data would arrive at each of the bit latches and when all had settled and were stable, the clock or strobe would trigger all the latches simultaneously to capture the data. If some were earlier and some later, all would have to wait for that last bit to be ready. The range of arrival times for the individual bits became a major limiting factor on how fast the bus could ultimately run.

In high-speed serial systems, de-skewing is done electrically rather than mechanically. De-skewing can be done by mechanisms such as measuring the time-offset of each input and selecting a particular clock phase that best matches it. It is fairly easy to generate a range of clock phases to facilitate this.

This method in turn necessitates a circuit training plan in which the relationship between clock and data can be measured. As the arrival phases of the individual signals are identified, the optimal clock phase for each can be locked in. So, the issue of skew between differential pairs that are not within an individual pair has passed into the realm of non-issue.

Because perfect components, components with no time delay and no parasitics, come naturally to SPICE, it is very easy to set up a differential driver—two outputs with complementary signals. Of course, there are a few standard warnings. As in any modeling task, be sure to include appropriate parasitics. For example, the tool can quite easily implement a behavioral driver that has no capacitance to ground.

In the real world, such a thing will never exist. As is typical of driver models, the important things to get right are the output voltage or current swing, the rise and fall times, the impedance, and the capacitance. In addition, differential drivers have both common-mode and differential impedance, and these can be independent of each other. The point is, take care to get them right.

Differential Receivers
Just as SPICE doesn't inherently recognize differential drivers, neither does it recognize differential receivers. Again, you are typically going to have to build the model. It is fairly easy to do because primitives such as the voltage-controlled voltage source already embody most of the characteristics needed in an ideal differential receiver.

All the model needs is appropriate parasitics, termination impedances, capacitance, and so on, and you can use it as your receiver. At this time, non-linearities and dynamic range will not be covered because the target of this book is the interconnect circuitry rather than what goes on inside the silicon.

Figure 7.8. A SPICE Ideal Component to Monitor Differential Voltage

Signal level and phase arriving at the receiver are usually critical parameters in any high-speed link. Viewing the differential signal is easily achieved through use of an ideal voltage-controlled voltage source, as in Figure 7.8 above.

In the case of using such a device to monitor a differential signal, all parasitics are left off so that the source produces infinite impedance at the point of measurement, and the gain is usually set to one. As such, it is possible to make measurements in SPICE that cannot be made in the real world.

Alternately, many versions of SPICE have the capability to do math on signals, so the differential voltage can simply be defined as an equation. Placement of a physical probe on a line always adds parasytics.

At microwave frequencies, the added parasytics, indicated in Figure 7.9 below, are usually far too large to ignore. That makes it difficult to measure waveforms that exist on the line when the test probe is not present.

Figure 7.9. Parasitics Added for a Voltage Probe

Two solutions are possible. One is to get or generate a good model of the test probe, and run a simulation with the probe model in place to correlate what is measured with what is there when the probe is not present. An alternate is to use a receiver designed to measure the signal quality at its inputs. A third alternative that actually works well in the frequency domain is to electrically characterize the parts, packages, and so on and calculate the result.

Differential Transmission Lines
Almost everything can be modeled. Recall the "T" line that came with the original SPICE implementations. This was an ideal transmission line. It had no loss.

When it was used, you did not have to calculate an inductance-capacitance ratio that would yield the desired impedance and velocity; the "T" model made that unnecessary. It simply asked for the desired impedance and delay. That level of support for differential transmission lines does not yet exist in most SPICE tools.

Among the parameters that you might like to see in your modeling tool is the ability to accept a transmission line definition in terms of differential and common-mode impedance, loss per unit of distance, and delay. The fact that such facilities as these are not there does not stop you from performing simulations; it merely adds a bit more work to include them by hand.

Of course, eventually all of this work might be bypassed by the enabling of S-parameter models in SPICE. Again, in an ideal world you would work entirely in the frequency domain. Components would be characterized by their S-parameters, and the response of the entire circuit response would be calculated by applying chaining to the various elements of the interconnect.

In this ideal world, circuit simulation would not even be needed. The response would be mathematically generated from measured or simulated frequency domain models  - S-parameters - and no iterative procedures would be required. Rather than simulation, there would be an extremely fast mathematical procedure.

Unfortunately, that ideal is not the world as it is. The problem is linearity. You cannot presume that the voltage and current sources are linear. They are not. The interconnect circuitry might be reasonably linear, but the silicon at the ends is nonlinear, at least to some degree.

That nonlinearity makes it inadequate to examine the response one frequency at a time. The actual response will have interactions between harmonics, and the response will be dependent on the amplitude and phase relationships between the harmonics. It becomes a modulation problem.

But the interconnect, the packages and circuit board traces, are likely to be linear in voltage response. The sort of thing that would make these parts nonlinear would be the presence of magnetic material. Without magnetic material, the parts are linear.

That linearity makes it practical to solve the response of the interconnect in the frequency domain using very fast analytic procedures and then add the impact of nonlinear drivers in an iterative, time domain, analysis. The capability of using blocks defined with S-parameters in time-domain simulations is just beginning to show up in SPICE tools.

One reason for interest in the frequency domain is this: Time domain simulations often rely on iterative methods and so are relatively slow. Frequency domain solutions can often be achieved through analytic methods and can be extremely fast and not iterative.

You can even see this in SPICE. Compare the time it takes SPICE to calculate the time domain response of a moderately complex L-C circuit with the time it takes to do a frequency sweep of the same circuit.

Corners and Bends
Corners and bends are unmodelable in the sense that SPICE does not have built-in mechanisms to deal with them. The handling of a corner in an individual trace is a bit more complicated than the handling of a bend in a differential pair. In the lower gigahertz frequencies, the impact of a corner in a trace is often so much less than the variability of the materials themselves—the manufacturing variables—that corners in traces can often be ignored.

As shown in Figure 7-10 below, a square corner adds a small amount of capacitance; the amount can be calculated with a field solver—not by SPICE. The added capacitance is sometimes the combined effect of added physical area and the reactance of ephemeral modes produced by the corner discontinuity. The usual way of modeling a corner in SPICE is to add a small discreet capacitor at that point in the transmission line, add a small L-C-L segment, or ignore it.

Figure 7.10. Capacitance Added by a Corner

Bends are another issue altogether. Here we are using the word "bend" to refer to a differential pair's corner. The handling of a bend has been already described, but more details may be useful. The main thing that a bend does, but is not recognized by SPICE, is increase emissions.

Conversion of some signal to common-mode by a bend can cause loss due to radiation, and SPICE doesn't know about radiation. Usually this is not a major cause of signal loss, but it can be a major cause of emissions.

Planar Waveguide
The region between two metal planes can be described as a planar waveguide. Examples of this type of waveguide, shown in Figure 7.11 below, exist on most circuit boards in the form of the region between power and ground planes, or the region between multiple ground planes.

Figure 7.11. A Planar Waveguide

Signals can be injected into this waveguide by applying a current that traverses the distance from one plane to the other. In other words, when the signal passes through a via that traverses this region, as in Figure 7.12 below, the signal couples into the planar waveguide, as in Figure 7.13 below. SPICE doesn't know about this. Though this phenomenon can couple resonances to the signal and cause signal problems, it also can usually be easily controlled.

Figure 7.12. A Via Traversing a Planar Waveguide.

Figure 7.13. Signal Injected into a Planar Waveguide

The cancellation of radiation by the presence of a complementary signal, the other side of the differential pair, significantly reduces the coupling to this waveguide. Radiation into this waveguide is a significant factor in the total loss of a via, and, in the case of a single-ended signal, is the major cause of signal loss. The way to deal with vias is to calculate an appropriate L-C model through use of a field solver and import that model into SPICE.

When a planar waveguide has a lot of vias and holes in it, energy leaks out or is extracted fast enough that its probability of becoming resonant is low. However, if the waveguide has few holes and vias, it can become resonant. This can cause a problem. The mechanism that couples your signal's energy into the waveguide also couples energy out of the waveguide.

The mechanism that converts part of your differential signal to common mode also converts common mode to differential energy. The end result of this chain is that if you have a plane that goes resonant, you are likely to see that resonance in the differential characteristics of the link.

This is yet another reason why you need to take care to minimize mode conversions by maintaining symmetry within your differential pair, as much as you can.

Plane-Splits
As with many other things examined above, SPICE does not know about plane splits, shown in Figure 7.14 below. Signal integrity and the emissions impact will require a different tool if you are concerned. Emissions apply primarily to the common-mode component of a signal.

The signal-integrity impact can be modeled by treating the gap as a pi-network of capacitors. But the value of the capacitors is found through use of a field solver. This is not too severe a problem if this rule is followed: never cross a plane-split with any high-speed signal.

Figure 7.14. A Signal Crossing a Plane Split

On the other hand, the impact of a narrow, say 10-mil wide gap, on the signal integrity of a differential signal is not going to be very significant. If the particular design is such that emissions is not a big concern, crossing plane splits is not too big a concern either.

One approach that can be used is to assign some penalty to crossing a plane-split and use that as a criterion to help minimize the number of plane-split crossings. That is, tell the architects and the layout guys that each plane split is equivalent to reducing the overall useful trace length by an inch. With features such as plane splits and vias, it is very hard to predict the precise impact.

They will increase loss, crosstalk, and emissions—but how much? Assigning an overall equivalent impact, such as claiming an overall usable distance reduction of an inch per, helps clarify the need to minimize such features in a high-speed pair. In some designs, this might be overstating the fact. In others it might not.

Vias
A via has two main impacts at high frequencies: it can cause signal loss through injection to the planar waveguide and it can act as a resonant stub at microwave frequencies. The coupling to the planar waveguide is linearly proportional to frequency; that is why this phenomenon may not have been noticed by those working in the lower few hundreds of megahertz.

As frequency increases, it becomes a much more serious issue. Again, a major advantage of differential signaling is that differential energy is far less impacted by this than is common-mode. When a differential signal traverses a planar waveguide through symmetrical and closely-spaced vias, it is almost exclusively the common-mode component that loses energy to the waveguide.

A good side to this is if a single-ended signal has to traverse the waveguide, and if the two planes are at the same potential, insert a second via near the signal, using it to short the two planes together.

Image current will flow through the shorting via and largely cancel the fields of the signal via. Losses will decrease. Surprisingly, this works even with differential signals. Adding a shorting via will decrease loss in the signal vias.

A fairly good model of a via can be constructed by R-L-C components where there is capacitor for each surface and reference plane, and an inductor for each region between. Such models can even be constructed with reasonable accuracy through use of lookup tables.

Of course, the entries in the lookup table are calculated with a field solver. Such a model may not show the impact of shorting vias, or their absence, but it can show the impact of resonant stubs in the via.

Electrostatic Discharge
It has already been pointed out that SPICE knows nothing about electromagnetic radiation. Neither does it know anything about electrostatic discharge (ESD). ESD typically involves non-linear phenomena and, though they can be modeled, they are seldom included in models designed for signal integrity applications.

There is a very high significance for signal integrity in one aspect of ESD. Pins that are designed to withstand ESD typically do so through the use of current shunting devices, often diodes. These components typically add significant capacitance to the protected pin. That capacitance shows up in circuit models as a value in parallel with the termination resistor.

This capacitance is often the biggest problem preventing really good values of return loss in microwave frequency ports. In typical systems, the better the ESD protection, the more capacitance. Because of this, very high speed ports often have very poor ESD protection. You need to keep this in mind whenever you handle these devices.

Next  in Part 3:  Modelable  Features of high performance designs
To read Part 1, go to "Unmodelable features of high performance designs"

Dennis Miller has worked in electronics since 1963. His early engineering interests and education centered on control theory and numerical analysis. Now his interests are signal integrity and numerical analysis. Since joining Intel Corp. in 1991, he has been instrumental in the development of Infiniband technology and similar high speed signaling technologies.

This series of articles is based on material from Designing High Speed Interconnect Circuits," by Dennis Miller, used here with the permission of Intel Press which holds all copyrights. It can be purchased on-line.