Until today, the performance of a processor has primarily been measured by the speed of its clock. The vast majority of integrated circuit (IC) designs have been based on a synchronous architecture, which is governed by a global clock. This architecture has become so ubiquitous that it is considered by many to be the only way to design digital circuits. There is, however, an altogether different design technique that is just now coming to the forefront: asynchronous design.

The main driver for this is the state of silicon technologies. As silicon geometries shrink below 90 nanometers, power reduction has become the top priority. Because asynchronous design offers lower power and more reliable circuits, it has been proposed as a way to address this requirement.

Asynchronous design has been avoided in the past for many reasons, the most important being the lack of a standardized tool flow. To deliver devices quickly, IC design teams use high-level programming languages in combination with electronic design automation (EDA) tools that speed tasks such as logic design. If such tools were available for asynchronous design, we would likely see more devices with asynchronous logic components.

In the past, most asynchronous designs were small circuits used to complement synchronous circuits. Larger asynchronous devices have appeared recently, but these devices often targeted niche markets such as embedded sensors.

We believe that the opportunities for asynchronous logic are far greater than past devices suggest. In this article we make the case for a general purpose digital signal processor (DSP) core based entirely on asynchronous logic. We reveal many benefits, both for the IC designer and the end user.

Synchronous vs. Asynchronous
Synchronous design is the de facto technique for digital design today. This methodology has been highly refined and the design tools are highly evolved. Synchronous design offers a standard flow—based on high-level languages— that enables rapid development. Synchronous design also provides an easy way to scale performance. Designers can create faster versions of a design by simply increasing the clock frequency.

Synchronous logic is broken down into asynchronous logic stages surrounded by flip-flops (also known as latches). These stages perform operations and pass the result on to the next stage. Figure 1 presents a simplified model of a single stage. The flip-flops store the current state associated with the logic. When a clock signal arrives, the flip-flops update their values, allowing new data to enter the logic. The asynchronous logic then calculates the new state of the circuit. For example, the logic cloud could perform an addition or multiplication.

Figure 1. Simplified diagram of a synchronous logic stage

In an asynchronous cirucuit, the logic stages are modified to remove the clock. The basic building block for this architecture is shown in the Figure 2. Instead of a clock controlling the latches, the logic stage provides a completion signal to let the following logic stage know that a new output is ready. The timing of the completion signal depends on the specific operation of the logic. For example, the logic may be able to achieve early completion for certain combinations of input signals.

This local delay control is the reason for the robustness of asynchronous circuits. Since the logic controlling timing is near the computational logic, it will match the computational logic's response to changes in voltage, process speed and temperature.

Figure 2. Simplified diagram of an asynchronous logic stage

There are many different approaches to asynchronous design, but the main theme is that the circuit is not governed by a single clock. Asynchronous logic is often used to solve specific problems with specific circuit designs. However, it is possible to use asynchronous logic as the basis for a complete DSP core.