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Understanding Crypto Performance in Embedded Systems: Part 2
Standards & Industry Practices for Measuring Cryptographic Performance



Embedded.com
Measurement Configuration #3. Shown in Figure 6 below is a security measurement performance of a configuration containing MPC8349A with the 32-bit e300 Power Architecture core, and SEC 2.4, and the following parameters:

MPC8349EA MDS
e300 core at 666 MHz, DDR at 333 MHz data rate, and SEC at 166 MHz
OS: Linux 2.6.11
IPsec stacks: StrongSwan, OpenSwan, Mocana, all running 3DES-HMAC-SHA-1

The chart compares StrongSwan and OpenSwan with Mocana. Mocana provides the highest throughput at all packet sizes. The Mocana performance advantage vs. the second-best implementation (OpenSwan in this case) is approximately 1.3x.

Figure 6. MPC8349EA IPsec Performance

Measurement configuration #4. Shown in Figure 7 below is the security performance for the MPC8360E, which contains the 32-bit e300 Power Architecture core, and SEC 2.4. These are the parameters:

MPC8360EA MDS
e300 core at 666 MHz, DDR at 333 MHz data rate, QUICC Engine at 500 MHz, and SEC at 166 MHz
OS: Linux 2.6.22
IPsec stacks: StrongSwan (uni-directional), Mocana (bi-directional), both running 3DES-HMAC-SHA-1

The chart compares StrongSwan with Mocana, with CPU utilization information. For this particular device, StrongSwan slightly outperforms Mocana at the smallest packet sizes. This may be due to a measurement difference (uni-directional vs bi-directional testing).

For IPv4 forwarding, uni-directional performance at 64 bytes is 142 Mbps versus 114 Mbps. This suggests that if the StrongSwan IPsec performance had been measured bi-directionally, Mocana would have outperformed StrongSwan, which is consistent with measurements on other devices.

Another unusual datapoint is the Mocana CPU utilization at 1456 bytes. CPU utilization should have continued to drop. CPU utilization is a calculated number, and it is possible that CRC or other Ethernet errors exceeded .001 percent, depressing the measured throughput. Because the Ethernet frames were dropped after IPsec processing, the CPU appears to have done more work that it actually did.

Figure 7. MPC8360E IPsec Performance

Measurement configuration # 5. Shown in Figure 8 below is the security performance for the MPC8379E PowerQUICC II Pro integrated communications processor, which contains the 32-bit e300 Power Architecture core, and SEC 3.0. These are the parameters:

MPC8379E RDB
e300 core at 666 MHz, DDR at 333 MHz data rate, and SEC at 110 MHz
OS: Linux 2.6.23
IPsec stacks: OpenSwan, Mocana, both running 3DES-HMAC-SHA-1

The chart shows the Mocana NanoSec IPsec stack as having higher throughput at all packet sizes. The Mocana performance advantage over OpenSwan is approximately 1.4x at 64B. This delta is relatively constant until the SEC begins to become the performance limiter, at which time OCF closes the gap.

Figure 8. MPC8379E IPsec Performance

Note that in order to perform a true "apples to apples" comparison of OpenSwan and Mocana, the MPC8379RDB board, which currently restricts SEC frequency to 110 MHz (compared to 166 MHz on most other 83xx products), was used.

OpenSwan data measured on a different board without this SEC frequency limitation shows the MPC8379E IPsec performance to be approximately 13% better across all packet sizes than the results shown in the figure, reaching approximately 560 Mbps at large packet sizes. It is reasonable to assume that the Mocana results would be 13 percent better at all packet sizes as well if the SEC were running at 166 MHz.

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