8051
The 8051 architecture supports two low-power levels (idle and power down). These modes are activated by setting the IDL or PD bits in the power control register PCON at the address 0x87. Writing to the IDL or PD bit stops the CPU immediately and must happen with interrupts enabled, otherwise the 8051 locks-up. This means that it's impossible to transition to one of these modes atomically. Any enabled interrupt can preempt the idle processing after the interrupts are enabled, but before the idle mode is entered. Clearly, the 8051 requires a different technique than those discussed so far.

This other technique is to invalidate the idle mode transition in every interrupt. So, if an interrupt preempts the background loop just before the indented transition to idle, the ISR will disable the transition. After the interrupt returns, the idle mode is not entered.

One way of implementing this technique on the 8051 is to shadow the PCON register allocated in the 8051's bit-addressable memory (bdata). Let's call this variable PCON_shadow. Listing 8 (for the Keil C51 compiler) shows how the background loop uses the PCON_shadow variable.

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The background loop sets the IDL bit only in the PCON_shadow variable when the interrupts are still disabled. Then, interrupts get enabled and the register PCON is restored from the shadow. It's important that the PCON register's update occurs in one machine instruction. As it turns out, the simple assignment of a bit-addressable variable to the special register, such as PCON, can be accomplished in one instruction--MOV 87H,20H.

The PCON shadow must be updated in every ISR that can produce work for the background loop, as shown in Listing 9. Note that the 8051 clears the IDL/PD bits in the PCON register before entering any interrupt, so these bits are guaranteed to be cleared in the shadow register when it's updated from PCON in the interrupt context.

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