The PLDesigner development system will be supplied by the leading electronics design system vendor, Mentor Graphics (Beaverton, Ore.). Since Mentor has selected Minc as its sole PLD design tool source, we may trust that PLDesigner really works.

Describing your function
The three most prominent PLD HDLs are found in PALASM, CUPL, and ABEL. PALASM, the first development system for PLD design, was supplied free by Monolithic Memories. Unfortunately, it could only design Monolithic's own PLDs. (Monolithic Memories is now a part of Advanced Micro Devices, Sunnyvale, Calif.)

CUPL is similar to PALASM and is available from a number of PLD vendors. A $50 starter kit containing the full CUPL program (but only configuration files for four PLD architectures) is available from Texas Instruments (Austin, Texas).

ABEL is the most flexible of these development systems. Although similar to PALASM and CUPL in the way it's used, ABEL supports many PLD architectures and some more advanced HDL commands. Unfortunately, it's still necessary to select the PLD architecture into which you want to compile the functional description and declare the pin usage for that PLD.

Listing 1 is a complete HDL program to generate a PLD for controlling the traffic lights at an intersection. Written in ABEL's state-machine format, the listing illustrates the main features of PLD HDLs.

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The first paragraphs contain the header information--device naming, device type, pin declarations, and include files. These are followed by a macro that forces the program into a known state when a RESET signal is applied. Though not absolutely necessary, this feature assists with power-up and test situations. And it's free; since there are unused pins on the chip, we might as well use one for initialization. Other pins could be used as sensor inputs to switch the traffic light only when a car is waiting at a red light.

The state descriptions cycle the traffic lights in an obvious manner. The last state description uses a compiler directive to generate four identical states that are stepped through sequentially to create a four-clock-period delay.

Other HDL structures
When the description is entered, ABEL compiles the HDL into the target PLD architecture and automatically generates a test vector file for the part. Because ABEL is linked to a full-logic simulation system called DASH, the entire hardware configuration can be validated in the same design environment. The generated fusemap files that are used to program the PLDs are also in a standard format, JEDEC, that can be used by many other CAE systems. For example, Logic Automation (Beaverton, Ore.) provides software that turns JEDEC files into behavioral models.