If we tried to compile Listing 1 as it stands, we would get at least one error message. The PLD architecture we've specified in the header field (p16r8) contains only eight register bits, and there are 10 states in the system.

It's not difficult to reduce the number of states used by the traffic-light controller to eight. The four register bits used in the four-stage delay can be reduced to two register bits by building a simple two-bit counter. Listing 2 shows how this can be done and presents the other two HDL structures supported by ABEL: truth tables and Boolean equations.

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Truth tables are the most intuitive way to capture a function such as the one we seek and are particularly suitable for describing complex bus decoding and encoding properties. ABEL also supports vector signal descriptions to permit bus modeling.

Listing 2a shows how two register bits are stepped through the binary sequence {0, 0}, {0, 1}, {1, 0}, {1, 1} to create a four-stage counter. Listing 2b illustrates an equivalent truth table reduced to a pair of Boolean equations. The equations may be further reduced to a pair of shorter equivalencies as shown in Listing 2c. The same function may also be described in a state machine in a somewhat lengthier manner (Listing 2d).

State-machine, truth-table, and Boolean descriptions in ABEL can be intermixed with schematic descriptions. This flexibility allows the programmer and hardware designer to work in the design description medium most suited to the task at hand.

ABEL is supplied by Data I/O (Seattle, Wash.), the leading vendor of device programmers. Data I/O also supplies DASH for schematic capture and simulation and PLDtest for automatic test-pattern generation.

Switching environments
HDLs are similar to general-purpose programming languages, the essential difference being that HDLs offer declarative extensions and special data types. Both features are illustrated in our ABEL examples.