FPGA device families from Altera
Table 2 lists FPGA device families from Altera in different cost categories. This table summarizes cost/performance data for over 100 FPGA devices (including various speed grades for each specific device). Note that details regarding each FPGA family (interface capabilities, internal memory architecture, and versatility of DSP resources) have been excluded from this summary. Moreover, the MMAC performance estimates are based on clock frequencies which are achievable given an overall resource utilization of 70 percent.

Also note that Table 2 does not identify MIPS performance values. A designer may include one or multiple Nios II processors in the FPGA depending on the available resources (registers and memory). However, defining a MIPS performance value for the FPGA as a whole is impossible because the use of an embedded processor (and its specifications) is design specific. Finally, it is important to note that logic resources and registers in the FPGA may be used to create additional signal processing resources to increase the MMAC performance.

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Table 2. Various FPGA device families from Altera sorted in different cost categories.

Table notes:
(1): Costs were obtained from www.altera.com in Jan 2008. At this time, the pricing for only one device, EP3SL150, was available in Stratix III device family.

(2): MMAC is defined as the number of fixed-point 32-bit or single-precision floating point multiply-and-accumulate operations that can be executed in units of millions per second. MMAC performance values increase by a factor of 4x for 16-bit operations.

(3): Assuming a clock frequency of 120MHz for Cylcone II and Stratix II and a clock frequency of 165MHz for Cyclone III and Stratix III devices. The overall resource utilization is estimated to be 70%. Note that higher resource utilization and performance is achievable in the FPGA.

Choosing FPGAs and/or DSPs
FPGAs and DSPs are different devices, and they were created for different purposes. DSPs were created to provide an optimized platform for signal processing algorithms implemented in software, while FPGAs were initially created for providing glue logic. Over time, DSPs and FPGAs have grown in performance and resources, and they now provide solutions in overlapping markets. Both have application areas in which they are the optimum solution. For example, FPGAs are by far the superior choice for networking applications that move traffic at Gigabit/second data rates. DSPs are the superior choice for video applications such as surveillance. However, there are many overlapping application space for these two devices.

In previous sections, we looked at the cost-performance values for DSPs and FPGAs. Table 3 summarizes these comparisons in three different MMAC performance categories: Low, Medium and High. Table 3 also groups devices according to their cost. For example, Medium-performance devices are sub-categorized into those costing $10~30, and those costing $30-100.

This table shows minimum cost/performance values. Note that FPGAs and DSPs differ in their functionality and features. These features must be kept in mind while considering their cost/performance values. Blindly choosing an FPGA its cost advantage (which can be as low as 0.2 cents/MMAC) would be a mistake.

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Table 3. FPGA/DSP comparison summary.

Table Note: MMAC is defined as the number of fixed-point 32-bit or single-precision floating point multiply-and-accumulate operations that can be executed in units of millions per second.

In order to put DSP and FPGA features in contrast, one can use Table 3 and Table 4 as guidelines for choosing between FPGA and/or DSPs. The decision process shown in Table 4 considers application-specific DSP features. DSPs often come with bundled features (see Notes for Table 1) that can translate into cost savings. Therefore, a DSP with application specific features has an advantage over an FPGA with similar cost/performance value. Table 4 reflects this advantage.

Table 4. Guideline for choosing DSP and/or FPGA.

Table Note: MMAC is defined as the number of fixed-point 32-bit or single-precision floating point multiply-and-accumulate operations that can be executed in units of millions per second.