Optimal on-chip power network design
Simple examples simulated in π-fp illustrate a beneficial aspect of total power integrity investigation, the trade-off between wire width and power bus spacing in the global power distribution network. The simulation netlist and stimulus current profile employed in an example whose results are shown in Table-1 follow below. This example has been run on Anasim's π-fp, a tool developed for total power integrity studies and power integrity aware floorplanning. Note that such qualitative studies on TPI are carried out very early in the design cycle, and are meant to assist IP Core and chip designers in arriving at an initial floorplan that is correct by design and optimized for metal resource usage, block placement, and power network noise.

In the above simulation input, the single line 'Gchip1 0.5 0.5 0.0010 0.0100 0.020 10e-9 10e-9' describes a power grid that is 5mm by 5mm in area, power grid wires of 10m width and 100μ bus pitch, 20mΩ wire sheet resistance, and distributed electromagnetic properties of 10nH/cm wire inductance as well as 10nF/sq. cm capacitance. This simplicity in power grid description, unavailable in traditional SPICE, is key to orders of magnitude faster true-electromagnetic simulations in π-fp s 'what-if' analyses.

A current source region 50μ by 50μ in area, located at (2mm, 2mm) in the physical layout and ramping up to 500mA in 100ps as defined in file 'ramp.txt' is used as stimulus in the experiment.

Table-1: Maximum voltage droop with power grid dimensions

Results from this qualitative experiment indicate that increasing wire width has minimal benefit in total power integrity that considers on-chip inductive voltage droops along with the traditional IR Drop. On the other hand, decreasing the power bus pitch with thinner wires provides substantial benefits in grid voltage noise. This finding is, in fact, related to known signal integrity improvement techniques. In accordance with this simple result, published research on power network optimization and the impact of on-chip inductance on power distribution network design claims as much as 30% improvement or reduction in metal area usage for power grids in the 90nm process, and approximately 60% improvement in the 45nm process with accurate modeling of on-chip power grid inductance.

Published research also indicates that this type of on-chip inductive effect becomes significant for load current edge rates at or below 100ps. In this example noise was reduced by increasing the number of transmission lines in the periodic grid. We find that an increase in the number of parallel inductors (with approximately the same inductance) is an effective way to reduce overall grid impedance in systems with high edge rates, and, in general, SPICE power grid analysis is much more difficult when inductance can no longer be ignored. Noise propagates out from the source at a velocity given by:

Where L is inductance per unit length of transmission lines in the grid and C is capacitance per unit length. This capacitance can be very large on-chip as it includes the capacitance of every component connected to the main current carrying bus (including the capacitance of many other wires on the lower layers). In a uniform, periodic grid, the capacitance per unit length is given by C=sC_A where s is the periodic space (bus pitch) and C_A is capacitance per unit area. Thus, wave velocity is given by

This means that, when we reduce noise levels by increasing the number of grid wires (reducing the pitch s), we also change the overall noise distribution by increasing the wave velocity. Conversely, when we reduce noise by increasing capacitance, we reduce wave velocity. We can see this effect by modifying the load current in the previous example to the profile shown in Figure 1. π-fp simulation results using this profile are shown in Figures 2 and 3. Again, we see significant overall noise reduction when the same metal area is used for a larger number of parallel transmission lines. However, the reduced grid impedance also has the effect of increasing the rate at which the noise wave front spreads out across the chip. This wave combines (is superposed) with waves propagating from other sources to produce the overall chip noise. Waves from each source interfere constructively and destructively in different parts of the grid. This type of noise distribution can not be predicted using a static analysis or dynamic IR drop tool as it is the result of complex interactions between edge timings, block placement, grid impedance and variable wave velocities (caused by variable capacitance per unit area in different parts of the chip). Again, this type of analysis is best done using tools that perform realistic simulations in minutes rather than hours or days. This makes it possible to complete the large simulation based experimental designs, covering the large parameter space (capacitance, width, space, placement etc.) required for this type of complex power grid design, within a reasonable timescale.

1. Triangular load current profile for grid noise investigations.

Viewed from another perspective, critical metal resources for routing and compact SoC physical design can be freed through total power integrity analyses of chip floorplan and power grids. Moving beyond IR Drop based design, we can not only improve verification of on-chip noise, enabling low energy design, but also optimize the SoC floor plan, improving routing and corresponding signal integrity, saving area, cost, and potentially, total design effort by minimizing synthesis and floor plan iterations.

2. On-chip power noise distribution for grid wire width 20um and periodic space 100um.

3. On-chip power noise distribution for grid wire width 10um and periodic space 50um.

4. Superposition of power noise from two sources (wire width 10um, pitch 50um).

Figure 4 shows superposition of power network response to two loads. Here, cumulative voltage droop in between the two load regions is seen to be substantially higher as compared with figure 3. Additional capacitance is added in the region marked C1, and voltage droop and noise propagation can be seen to have reduced here. Such effects, and electro-migration by current crowding through low-inductance, higher-resistance pathways (with low resistance, longer loop, global pathways in parallel) are entirely missed out in IR Drop based or other analyses that ignore inductances or time/space distributed loads.

Moving beyond IR Drop to Total Power Integrity
Power integrity related failures tend to fall into the occult (inexplicable) basket for most digital and VLSI designers. In part, this is because power supply non-idealities have not been as clearly quantified as signal-to-noise ratio in signal integrity, and partly because most circuits and chips are designed to exhibit very good PSRR, or power supply rejection ratio, minimizing attention paid to power supply integrity. It used to be common to specify a power supply with 10% variation, with power simulations and verification conducted at a system or package level assuming a certain power consumption profile in the chip supported by such system or package. Such luxuries are no longer available in the nanoscale regime. Chip-Package co-design has become a gating aspect of product design and development.

Power supply voltage values are specified with a much tighter variance band, in part because achieving performance with increasing device variations is that much more difficult with substantial supply voltage variations. In other words, PVT methodology is seeing so much 'P' variation with no reduction in 'T' variation that the budget for 'V' variation is that much lower. Energy consumption is also a critical and product-differentiating design constraint; the one dominant variable that impacts energy is voltage, which must be reduced to the absolute minimum possible. Such tuning of operating voltage can only be done if the noise band anticipated within the chip embedded in the system is very well understood. There is clear and present motivation to move to advanced, true-electromagnetic, total power integrity investigations. There also is clear and present danger that if such a transition is delayed, there could be significant yield impact in nanoscale SoC's that could be hard to debug, and even harder to correct absent comprehensive understanding or verification methodology.

Nevertheless, the EDA industry is known to move cautiously. Dynamic IR Drop, for example, is said to have taken more than 5 years before being accepted as a necessary aspect of chip power integrity and decoupling capacitance sufficiency verification. In the case of comprehensive on-chip inductance inclusion, the barrier is even higher, given that all of today's device extraction techniques focus on polygonal R, C and L extraction, and L extraction requires understanding of current return pathways which makes it all the more challenging. Advanced modeling techniques such as PEEC have shown some promise, but simulations with any large number of inductors tend to take many hours or days, with convergence and accuracy problems, and constructing multiple PEEC-based models for different grid architectures is very time-intensive. Therefore, despite multiple research results having shown that including on-chip inductance and L*di/dt noise results in significantly better optimization of metal resources, the EDA industry has been hesitant to move forward with this essential advancement to front-end total power integrity verification and optimal floorplanning.

Fortunately, solutions to ease of inductance inclusion and rapidity in early 'what-if' analyses have been developed. One needs only to understand that trade offs exist between degrees of freedom and design/ verification capability just as it is with optical proximity correction and restricted physical design rules, or with nanoscale device sizing and predictability of device parameters. Employing restricted design and symmetry rules to power network synthesis as well, one can not only ensure low loop inductances, but also develop simplified representations of partitioned on-chip power networks that facilitate greatly reduced computational complexity for true-electromagnetic (Maxwell's field equations based) dynamic simulations. This is the underlying technology in Anasim's power integrity aware floor planner, π-fp, that represents power distribution grids as surfaces with simulation complexity independent of the number of wires or circuit/capacitance blocks within the areas represented.

From a methodology transformation perspective as well, π-fp provides a non-disruptive pathway to benefiting from comprehensive, true-electromagnetic simulations on block and chip power distribution networks and floorplans. Working with conceptual floorplans, power grid dimension specifications, limited process information (sheet resistance and capacitance), and intra-cycle block-level load current profiles available from pre-processors to Dynamic IR Drop analysis, this tool provides spatio-temporal, dynamic, total power integrity information that permits optimization of power distribution grid dimensions, and circuit block / decoupling capacitance physical layout and placement. Optimization results may then be manually input into the physical design flow, with static IR Drop analysis detecting and eliminating any current or electro-migration hot-spots as physical layout matures.

The future could see true-electromagnetic simulations replace Dynamic IR Drop " or should it be now?

About the Authors:
Raj Nair is the co-founder of Anasim Corporation and a well known consultant.
Donald Bennett is also a co-founder of Anasim Corporation.