Review: Part I, Part II, Part III., Part IV, and Part V.

Summary
Batteries have only improved their capacity about 5% every 2 years. As a result mobile devices need to become more power efficient to close the performance energy gap.

Success of power efficient mobile devices requires system-level optimization choices. However, a holistic approach consisting of systems design, software, architecture, circuit design, and manufacturing processes is required to tackle the low power challenges.

Further expansion in the specialization of device structures will proceed over the next few generations of CMOS, with increased emphasis on new materials and structures. This will maintain the momentum toward power, performance, and cost benefits that, until recently, had been simply benefits of scaling.

Further gains from scaling of traditional planar CMOS devices will be very difficult, limited by leakage and switching power considerations. The planar MOSFET will be challenged by multi-gate devices. Multi-gate devices offer an alternative path to increase the functions/unit silicon by providing better transistors for existing circuits and making new applications feasible using the novel features made possible by these devices.

As transistors get smaller, parasitic leakage currents and power dissipation become significant issues. By integrating the novel three-dimensional design of the tri-gate transistor with advanced semiconductor technology such as strain engineering and high-k/metal gate stack, an innovative approach has been developed toward addressing the current leakage problem while continuing to improve device performance.

The integrated CMOS tri-gate transistors will play a critical role in energy-efficient performance philosophy because they have a lower leakage current and consume less power than planar transistors.

Because tri-gate transistors greatly improve performance and energy efficiency, they enable manufacturers to extend the scaling of silicon transistors. Tri-gate transistors could become the basic building block for microprocessors in future technology nodes. The technology can be integrated into an economical, high-volume manufacturing process, leading to high-performance and low-power products.

The FinFET provides the most likely candidate for succession, enabling continued growth in density and reduction of cost for SoCs, even as the industry approaches nearing the atomic limit. The trends in benefits to density, performance, and power will be continued through such innovations. Rather than coming to a close, a new era of CMOS technology is just beginning.

The major challenges to sustain CMOS scaling include the economics and complexity of new materials and processes. Product innovation will be enhanced by process development and package contributions. As mobile devices do more in less space, so do their enabling technologies. SoC packaging is no exception. Packaging technologies provide benefits not only to end device manufacturers, but also to consumers. Manufacturers gain the benefit of high levels of integration so that they can use increasingly sophisticated electronics without adding bulk. This integration also saves board space, so that more functionality, including cameras to multimedia players and radios, can be packed into mobile devices. Consumers also see the benefit of smaller mobile devices with more features, such as smartphones, PDAs, and portable media players.

While short-term packaging needs will be met by incremental improvements of current generations of technology, future packaging needs require new technology to meet evolving engineering and market demands. Each step along the path from SiP to PoP represents improvements in these two areas. Right now, each of these packages fit unique niches. For example, if size is most important, then stacked die will yield smaller packages. Moving into PoP may actually increase board space, but improves cost structure.

SoC, SiP, and PoP all provide varying degrees of functional and systems integration but are limited to conventional substrate design and manufacturing capabilities as well as traditional interconnect technologies such as wire bong and flip chip. SoC can become prohibitively expensive. However, the different waves of packaging techniques have helped produce decreases in system size that support Moore ' s law. Innovative packaging technologies like SiP and PoP are viewed as a critical enabler in helping continue this trend and fill what is called the packaging gap.

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About the Author
Findlay Shearer holds a B.S.E.E. from Glasgow Caledonian University and a M.S.S.E. and M.B.A. from University of Texas at Austin. He is currently a Senior Product Manager in Freescale Semiconductor, Inc.

Printed with permission from Newnes, a division of Elsevier. Copyright 2008. "Power Management in Mobile Devices" by Findlay Shearer. For more information about this title and other similar books, please visit www.elsevierdirect.com.