For example, in Lattice's ispMACH 4000ZE CPLD, all the I/O pins within a block share a common Power Guard (Lattice's feature name for input gating) enable signal, called a Block Input Enable (BIE) signal. BIE can be internally generated using macrocell logic, or from an external source via a user I/O or input pin. For additional design flexibility, there can be as many block input enable signals as there are blocks on the device, from 2 to 16. Two or more of these can be combined together to form just one user enable signal.

Using the 64-macrocell ispMACH 4064ZE device as an example, utilizing Power Guard on all but two active inputs reduces the dynamic current by 99%. As shown in Fig 3, dynamic I_CC is reduced from 2.9 mA to 26 µA.

3. Power consumption using power guard.
(Click this image to view a larger, more detailed version)

Some CPLDs also support the ability to further reduce I/O current and total system power by selectively enabling certain I/O pins "high" or "low" on a per pin basis via software. Input hysteresis in the range of 250 mV to 500 mV typically is used to reduce noise and improve signal integrity of slow varying input signals.

Most handheld systems require LVCMOS interfaces based on the primary system power supply, typically 1.8V. These systems require interfaces to other devices that operate using either TTL or LVCMOS standards. All CPLDs available today have separate core supplies and I/O power supplies enabling support for 1.5V, 1.8V, 2.5V, and 3.3V LVCMOS operation. CPLDs such as the ispMACH 4000ZE are also able to interface with legacy 5V LVCMOS devices.

Board space
As handheld product size continues to shrink, designers must integrate more logic functions within very small board space. CPLDs today are offered in ultra-small space saving packages including chip scale BGA (csBGA, 0.5-mm pitch) that require only 25 mm² or 49 mm² of board space, compared to traditional thin quad flat pack (TQFP, 0.8mm pitch) packages that require 100 mm² or 196 mm² of board space.

Ideal for space-constrained applications, these packages reduce board space by more than 75% compared to traditional TQFP packages, simplifying board routing and reducing total system cost. Fig 4 shows ispMACH 4000ZE csBGA packages. BGA packages also have lower thermal resistance values (typically 10 degrees per watt) than TQFP or PQFP packages (20 to 40 degrees per watt), making them a better choice for lower power dissipation and device reliability.

4. Small form factor packages for handheld applications
(ispMACH 4000ZE CPLD)

System Integration
By reducing the number of board components, the total system cost can be reduced. Manufacturing costs, including assembly, packaging and shipping costs, add to total board cost when several board components are used. Also, the more components that are on a board, the higher the failure rate, due to residue between solder balls and other random failures.

Lower power consumption can also be achieved by using fewer components. Today, low-power CPLDS are used to integrate external clock sources and standard discrete logic devices, such as the 7400-series logic devices. A single CPLD can be used to integrate multiple discrete 74xx devices and also perform additional functions such as I/O expansion, voltage level translation and timing control.

In addition to supporting logic densities from 32-256 macrocells for system integration, the ispMACH 4000ZE CPLD also features an on-chip user oscillator and timer that can be used for power-up sequencing, keypad scanning, and display controller functions. The typical output frequency of the oscillator is 5 MHz; however, the frequency can be further divided by 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits) to operate at even lower frequencies. The benefits of using an integrated oscillator within the CPLD include board cost reduction, inventory management simplification, and minimal obsolescence risk, which is usually associated with discrete devices. Table 1 shows a comparison of the latest generation of CPLD families that can be used for handheld systems.

Table 1. Comparison of CPLD families for handheld systems.

Conclusion
CPLDs are increasingly being used in handheld applications. Offering zero standby power options, ultra-small space saving packages, and enhanced system integration capabilities, CPLDs offer designers a low-cost system solution with significant advantages compared to traditional implementations using ASICs and ASSPs. In addition, CPLDs enable designers to offer products with the new features and capabilities demanded by consumers, and to get them to market more rapidly and with less risk.

Shantanu Dhavale is product marketing manager at Lattice Semiconductor. In this role, Shantanu is responsible for all product marketing and consumer marketing aspects of Lattice's FPGA and CPLD solutions.

Prior to joining Lattice, Shantanu held marketing and engineering positions at Altera, Philips Semiconductors and Integrated Device Technology. Shantanu holds a bachelors and masters degree in electrical engineering from Arizona State University and an MBA from San Jose State University.