The rapid proliferation of handheld products, including mobile phones, personal media players, handheld video game players, and digital still cameras, continues to put increasing pressure on system designers to deliver new features and capabilities in a compressed time-to-market window. According to forecasts from the market intelligence firm iSuppli Corp., core semiconductor revenue in this space is expected to grow from an estimated $26B in 2008 to $30B in 2012, a CAGR of 4 percent (core is defined by iSuppli Corp. as ASSPs, ASICs and PLDs).

Traditionally, the logic requirements for handheld applications have been addressed by Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs), and the use of programmable logic devices (PLDs) has been limited, due to the need for low standby power, small board space, and low cost. However, improved architectures that reduce power consumption, new packages for smaller form factors and lower cost per unit, are causing designers to choose PLDs due to their inherent time-to-market and design flexibility advantages over ASICs and ASSPs.

CPLD applications
Common applications for complex programmable logic devices (CPLDs) in handheld applications include power up sequencing, voltage level translation, timing control, interface bridging, I/O expansion, and discrete logic functions. A CPLD takes only a few microseconds to power up, which allows it to control the power up sequencing of other devices in a system.

CPLDs are also used to connect multiple devices that operate at different voltages within a handheld system. For example, a mobile phone requires a microcontroller to interface with peripheral devices, timer, and memory that operate at different voltage levels. The latest generation of CPLDs can interface with different voltage levels ranging from 3.3V to 1.5V, because they have a core power supply voltage (Vccint) that is independent of the output voltage (Vccio). Each I/O bank of the CPLD can be configured to operate at the unique voltage that is required to interface with the logic device. Fig 1 shows CPLD functions in a typical handheld system.

1. CPLD functions in a typical handheld system.
(Click this image to view a larger, more detailed version)

General purpose I/O expansion is another area where a CPLD can be used in conjunction with a microcontroller, ASIC, or ASSP to expand the total number of user I/Os. An additional advantage of a CPLD is that it allows a peripheral interface to be implemented and also be reprogrammed. CPLDs can also be used for interface bridging functions by connecting different I/O interfaces such as I2C, SPI and memory interfaces, as well as for implementing timing control for LCD panels within a handheld system.

Designers consider several factors when selecting a logic solution for use in handheld applications, including time to market, design flexibility, standby power consumption, board space, and system integration options.

Time to market and design flexibility
Shorter product life cycles challenge the designers of handheld devices to deliver the new products and features that are demanded by consumers. For high production volumes, ASICs may provide a lower price per unit; however, they have high non-recurring engineering (NRE) costs and long development times. If an ASIC does not function correctly, or if the product requirements change due to changes in industry standards or market demand, a new design must be developed. This redesign incurs significant NRE costs, which include engineering resources, new mask sets and software design tools. Furthermore, there is a considerable amount of time, usually several months to a year, between implementing the new changes to taping out the new device and going into volume production.

Compared to ASICs, ASSPs have lower NRE costs because they are used by multiple customers; however, they restrict the designers' capability to differentiate their products in the market.

CPLDs enable designers to develop, test and make design changes without incurring any mask costs or design penalty. Because CPLDs are reprogrammable, designers can make last minute bug fixes and product upgrades using software design tools, even when the devices have already been deployed in the field. As a result, designers are able to respond to changing requirements and standards and deliver new, differentiated products to the market very quickly, without having to go through any design or board re-spins.

Power consumption
CPLD power dissipation is usually split into two components: static and dynamic. Static power is power that is consumed when no signals are switching in the device. Dynamic power is power that is consumed when signals are switching in the device, and is proportional to the internal capacitance, switching frequency and switching voltage. Standby operation time is a critical design factor for handheld systems, because designers want to minimize the static power associated with logic in their designs in order to maximize the interval between battery charges or replacement. The maximum static power consumed by today's low power CPLDs is in the range of 10 to 150 µA, depending on the device's logic density.

In order to reduce total system power further, some CPLDs enable a user to selectively disable unused input pins (referred to as "input gating"). As shown in Fig 2, this feature consists of enabling a multiplexer between an I/O pin and input buffer, and its associated circuitry within the CPLD. When the enable signal is active, all inputs can be isolated, or guarded, so that if any of these inputs were toggled they would not cause internal pins to toggle. As a result, even if the I/O pins were toggling, they would not affect the internal dynamic power consumption of the device.

2. Power Guard in ispMACH 4000ZE CPLD.

For example, in Lattice's ispMACH 4000ZE CPLD, all the I/O pins within a block share a common Power Guard (Lattice's feature name for input gating) enable signal, called a Block Input Enable (BIE) signal. BIE can be internally generated using macrocell logic, or from an external source via a user I/O or input pin. For additional design flexibility, there can be as many block input enable signals as there are blocks on the device, from 2 to 16. Two or more of these can be combined together to form just one user enable signal.

Using the 64-macrocell ispMACH 4064ZE device as an example, utilizing Power Guard on all but two active inputs reduces the dynamic current by 99%. As shown in Fig 3, dynamic I_CC is reduced from 2.9 mA to 26 µA.

3. Power consumption using power guard.
(Click this image to view a larger, more detailed version)

Some CPLDs also support the ability to further reduce I/O current and total system power by selectively enabling certain I/O pins "high" or "low" on a per pin basis via software. Input hysteresis in the range of 250 mV to 500 mV typically is used to reduce noise and improve signal integrity of slow varying input signals.

Most handheld systems require LVCMOS interfaces based on the primary system power supply, typically 1.8V. These systems require interfaces to other devices that operate using either TTL or LVCMOS standards. All CPLDs available today have separate core supplies and I/O power supplies enabling support for 1.5V, 1.8V, 2.5V, and 3.3V LVCMOS operation. CPLDs such as the ispMACH 4000ZE are also able to interface with legacy 5V LVCMOS devices.

Board space
As handheld product size continues to shrink, designers must integrate more logic functions within very small board space. CPLDs today are offered in ultra-small space saving packages including chip scale BGA (csBGA, 0.5-mm pitch) that require only 25 mm² or 49 mm² of board space, compared to traditional thin quad flat pack (TQFP, 0.8mm pitch) packages that require 100 mm² or 196 mm² of board space.

Ideal for space-constrained applications, these packages reduce board space by more than 75% compared to traditional TQFP packages, simplifying board routing and reducing total system cost. Fig 4 shows ispMACH 4000ZE csBGA packages. BGA packages also have lower thermal resistance values (typically 10 degrees per watt) than TQFP or PQFP packages (20 to 40 degrees per watt), making them a better choice for lower power dissipation and device reliability.

4. Small form factor packages for handheld applications
(ispMACH 4000ZE CPLD)

System Integration
By reducing the number of board components, the total system cost can be reduced. Manufacturing costs, including assembly, packaging and shipping costs, add to total board cost when several board components are used. Also, the more components that are on a board, the higher the failure rate, due to residue between solder balls and other random failures.

Lower power consumption can also be achieved by using fewer components. Today, low-power CPLDS are used to integrate external clock sources and standard discrete logic devices, such as the 7400-series logic devices. A single CPLD can be used to integrate multiple discrete 74xx devices and also perform additional functions such as I/O expansion, voltage level translation and timing control.

In addition to supporting logic densities from 32-256 macrocells for system integration, the ispMACH 4000ZE CPLD also features an on-chip user oscillator and timer that can be used for power-up sequencing, keypad scanning, and display controller functions. The typical output frequency of the oscillator is 5 MHz; however, the frequency can be further divided by 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits) to operate at even lower frequencies. The benefits of using an integrated oscillator within the CPLD include board cost reduction, inventory management simplification, and minimal obsolescence risk, which is usually associated with discrete devices. Table 1 shows a comparison of the latest generation of CPLD families that can be used for handheld systems.

Table 1. Comparison of CPLD families for handheld systems.

Conclusion
CPLDs are increasingly being used in handheld applications. Offering zero standby power options, ultra-small space saving packages, and enhanced system integration capabilities, CPLDs offer designers a low-cost system solution with significant advantages compared to traditional implementations using ASICs and ASSPs. In addition, CPLDs enable designers to offer products with the new features and capabilities demanded by consumers, and to get them to market more rapidly and with less risk.

Shantanu Dhavale is product marketing manager at Lattice Semiconductor. In this role, Shantanu is responsible for all product marketing and consumer marketing aspects of Lattice's FPGA and CPLD solutions.

Prior to joining Lattice, Shantanu held marketing and engineering positions at Altera, Philips Semiconductors and Integrated Device Technology. Shantanu holds a bachelors and masters degree in electrical engineering from Arizona State University and an MBA from San Jose State University.