Assuming it takes approximately 1 minute to check and update each pin, the total time consumed through pin swapping alone would be 10,000 minutes or 166 hours. At a nominal cost of $50 per hour, the cost of this activity translates to over $8300 in labor costs and a delay of around one month in the development plan (see Fig 1).

1. As the pin count goes up, the cost of manually pin swapping FPGA devices increases significantly.

As an alternative to manual pin and data synchronization, several design tool vendors offer various add-ons which, together with their core products, form an 'integrated' solution. In proposing this, they view the propagation of FPGA data into board-level design processes as little more than an incremental change to existing processes. But it is a view that needs to be challenged.

Integrated tools consider electronics design to be a sequence of disparate design processes and the design data is localized to the process that creates it. Where data from one process is required by another process, it is made available through a separate 'bolt-on' utility that is responsible for parsing the data into the appropriate downstream format. Upstream data propagation, if available, is managed through another utility that performs the backwards conversion.

On the surface, purchasing add-ons to an existing design package may appear to be a good solution but a more detailed analysis reveals that it introduces considerable complexity to the overall design process. Because design data is stored locally to the processes that use it, data synchronization problems can actually compound rather than improve (see Fig 2).

2. Using a 'bolt-on' module or utility to manage FPGA data in a PCB design. Observe the added complexity that is added to the design flow.
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The old and the new: making pin and part swapping in FPGA designs a new, profitable reality
Given the apparent complexity and cost of managing pin swaps across designs that incorporate FPGAs, one option would be to admit defeat and retreat to the position of disallowing all pin swaps whatsoever. But that would forfeit one of the key benefits of using FPGAs.

On any non-programmable device, the high number of pins can create routing headaches but the exact opposite can be true of FPGAs. Having the ability to quickly and easily change the pins on which IO signals emerge from can have a dramatic improvement on the board layout and actually lead to a drop in the number of layers and complexity of the PCB. By using the programmable nature of the FPGA, much of the PCB routing challenge can be pushed inside the FPGA where it can be handled by automated tools.

So for designers to remain competitive while still holding onto their sanity, they need design tools that understand the challenges posed by pin swapping and synchronizing large-scale FPGA devices. They need a design approach that is in tune with the combined needs of FPGA and PCB development. They need an alternate approach to design that goes beyond existing methods.

In creating such a system, there are a number of features that it would need to offer. For example, existing design approaches effectively require the PCB layout expert to be familiar with the specifics of the FPGA device. This may be a reasonable expectation for non-configurable devices but the very fact that FPGA internals can be programmed means that the exact function of each of the pins will vary according to the application. It will therefore be impossible for the PCB layout expert to know which pins can and cannot be swapped purely from looking at the component's datasheet or pin out.

An alternate design system should empower the PCB layout expert to perform pin swapping without being expected to know the specifics of the FPGA design. Instead, the FPGA designer would specify which pins can and cannot be swapped and then embed that information into the design data. The PCB layout expert can then treat the FPGA as a virtual black box and use the embedded rules to guide any pin swapping that is necessary.

As this approach would require co-operation from the FPGA designer to input the relevant pin swapping rules, some assistance should be offered for this task. A mixture of information derived directly from the target FPGA device such as IO standards, IO banks, drive strength, signal names, etc, could all be used to help the FPGA designer quickly create the necessary pin swapping rules (see Fig 3).

3. Using the properties of the targeted FPGA device to assist with creating pin swapping rules.
(Click this image to view a larger, more detailed version)

Since pin swapping at the PCB level is largely a process of minimizing trace lengths and cross-overs, once the pin swapping rules have been defined, the actual process of performing the swaps could be readily solved automatically. Of course there will always be the need for some human interaction but on the whole, an automated pin swapping process would be desirable.

Finally, once pin swaps have been made, there remains the need to seamlessly propagate the relevant changes into the FPGA design where it can be checked and verified before final approval is granted (see Fig 4). Should timing or some other constraint be violated, the design tool should allow for further constraint information to be presented back to the PCB designer so that it can be incorporated into additional updates.

4. One approach to propagating pin swapping information between FPGA and PCB documents.
(Click this image to view a larger, more detailed version)

What to consider when selecting a design tool
Having embraced FPGAs and the opportunities they bring to electronics product development, design organizations need a design tool that goes beyond old design methods and offers improved ways to manage the growing complexity of high pin-count FPGAs. It is no longer sufficient to treat the board design and layout processes as being separate from the FPGA design process. Whilst they might be performed by different people, they are ultimately all part of a bigger product development process and need to be linked as such.