Introduction
Designers of consumer product ICs are faced today with the challenges of rapidly increasing complexity, a market with high expectations, and static price points. To stay competitive, design teams must find a way to reduce the cost and improve the efficiency of IC design. This dilemma has gone beyond the capacity of existing methodologies, and the industry is in urgent need of a new approach. Most agree that the solution to improving cost and efficiency is to move to a higher level of abstraction - but what is the best route to get there?

Algorithmic synthesis (AS) moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings. Deploying AS for this defining part of the IC not only pays immediate benefits, but can also be the critical first step in moving the complete design process to a higher level of abstraction. Once AS is established, the methodology can be used to drive verification and validation upwards too, followed by the hardware/software hand off. Using a step-by-step approach, AS can capture the whole of the IC design, at a level of abstraction capable of quickly handling growth in complexity.

A typical IC
A complex IC for most consumer applications comprises, at the highest level, four discrete types of IP:

• Application engines (video codecs, wireless modems)
• Star IPs (CSU, DSP)
• Connectivity and Control IP (USB, DMA)
• Memory

The application engine, or algorithm in silicon, is the most critical and time-consuming part of any IC design: critical because it defines and differentiates the end product; time-consuming because the algorithms are complex, the requirements exacting in terms of power, performance and area, and the algorithm changes significantly with each revision.

Complex application engines such as those used in multimedia, imaging, wireless, security and networking domains, are traditionally designed block-by-block, either by reusing previously designed blocks, or by creating new RTL blocks manually. The immense amount of time this latter step takes can force designers to re-use blocks and IP which are not specifically targeted at the current application in order to meet budgets and deadlines, resulting in less than optimal performance.

AS Methodology
AS enables designers to create application engines directly from sequential, untimed C algorithms. To deploy AS, the designer provides a C description of the algorithm, along with a C testbench and design constraints such as clock frequency and throughput. AS then automatically generates synthesizable RTL to fit these constraints. For algorithmically complex designs like application engines, AS results far exceed manual design results in terms of time and cost, without compromising performance.

Key Features of AS

• Architectural exploration for optimal design:
  Less time spent designing blocks means more time for architectural exploration. With AS, designers can evaluate alternative implementations, each of which can be modified and re-verified as often as necessary, just by changing the specified constraints. This enables them to find the design that yields optimal power, area and performance results.
• A complete verification and validation environment:
  it supports both RTL level verification and system-level validation using SystemC transaction level models.
• A single language from architecture to implementation:
  AS supports hardware synthesis from sequential languages to timed RTL. This means that the same language can now be used for hardware, software and system modeling.
• Possible re-use of IP:
  can be targeted against specific design criteria.
• The building up of a library of algorithms:
  these can be rapidly modified and deployed to meet new or changed performance targets in successive designs
• Smooth integration:
  the hardware generated is compatible with existing RTL and SystemC flows for rapid, uniform integration into ICs.

Benefits of using AS

• Best performance:
  extensive architectural exploration results in best performance, without major effort or expense.
• Reduced Design Time:
  AS requires less time for development and enables extensive IP reuse.
• Reduced area and power consumption:
  AS has been proven to reduce power/area by 10% or more.
• Reduced Verification and Integration Time:
  by using previously verified blocks and creating test benches to validate the RTL, AS significantly reduces time spent on this part of the flow.
• Flexibility:
  the advanced exploration capabilities also allow designers to react rapidly to changes in specification.
• Low risk implementation:
  AS can be proven on a small project initially, and then gradually extended to larger, more mainstream designs.

Moving to a complete AS usage flow
Once AS has been established at the application engine level and these kind of results have been achieved, you can set up an AS usage flow. After the scope and timeline for the initial project have been agreed, there are four stages that you need to follow to make this work successfully:

1. Create the architectural template that captures the required properties of the hardware.
   The traditional division between architecture and implementation means that the architectural design is based on simulation results and mathematical estimates, which are often not applicable once they are translated to the hardware. By using algorithmic synthesis to create an architectural template, the design architect can get a real performance estimate for each choice that he makes, ensuring that the architecture will meet all the hardware requirements before handing it over for implementation.
2. Define a code application to meet functionality and performance goals.
   During template creation, the design architect can explore all combinations of streaming interfaces, memories and wires to obtain the best mix for the defined constraints of the design. AS can take any of these combinations and generate RTL which can then be profiled for performance and functionality.
3. Fine-tune the code to meet area and power goals.
   The template also allows the architect to compare multiple partitioning and data movement schemes to identify the best implementation in terms of area, power and performance for any given algorithm.
4. Hand off the design for IC integration.
   Once the template has been simulated and shown to meet design requirements, it is ready for hand off for integration into the IC. During this hand off, the template essentially becomes a functional specification of the hardware to be built. The complete template can be simulated at the RTL level to ensure that it meets or exceeds the required design performance.

Actual example of using AS to accelerate design time.
The real life benefits of using AS to automate the creation of RTL and accelerate design time are demonstrated in the following example, which takes an ANSI-C algorithm and creates a fully functional design. The chosen application combines real-time color space conversion from RGB to YUV and a Sobel edge detector. The project was divided into the four steps outlined above.

1. Create the architectural template that captures the required properties of the hardware.
   Figure 1 shows the block diagram for the example application. A design architect creates the template of the design using this kind of block diagram, which captures at a conceptual level the division of computation and lays out the interconnection of blocks. During template creation, the architect explores different data communication paradigms between blocks to obtain the best combination to satisfy design constraints.

1. Color conversion and Sobel Edge Detector.
2. Define a code application to meet functionality and performance goals.
   After template completion, an implementation engineer takes the template from the design architect and fills in the functionality. As all data flows are explicit within the template, the engineer can achieve a functionally correct design notably faster than with a manual approach. After the template has been filled in with the necessary code to achieve functional correctness, it can be simulated and tuned to meet the design performance goals.
3. Fine-tune the code to meet area and power goals.
   The AS engineer focuses first on functional correctness and performance, because verification can be started as soon as functional correctness is achieved without waiting for the final RTL. Once the verification team starts to work on the design, an engineer using an AS flow can further optimize the code to reduce area and power consumption. This tuning does not affect verification, since the functional correctness of the design is always maintained.
4. Hand off the design for IC integration.
   The final RTL is delivered for integration after area and power optimizations are complete. The integration engineer takes the RTL generated by AS and quickly integrates it into the rest of the design. AS achieves rapid integration by supporting a standard set of interfaces, which allow the engineer to rapidly connect an AS-generated core with the rest of the IP in the system.

Results
In this example, the application took less than five minutes to generate RTL and less than ten minutes to generate a bitstream. AS enabled the engineers to go quickly from algorithmic code to fully functional designs. The ANSI-C based input allowed the team to work with a familiar coding language, which helped to reduce the learning curve, and made it possible to compare price and performance trade-offs before choosing the right part, without having to modify the application code.

Benefits of using AS across the whole IC design
Using AS to move your IC design to a higher level of abstraction has already been successfully proven and evaluated in multiple domains, including video and imaging. These are the typical results that have been achieved:

• 5x productivity gain:
  AS can reduce overall IC cycles between 10 " 40% depending on level of deployment.
• Power, performance and area results match best hand design results:
  

  AS's flexibility exploring different algorithms ensures optimal implementation.

• Adjustment to late changes in spec:
  means that users are able to meet deadlines with the most up-to-date spec available.

How Algorithmic Synthesis will help you to be more competitive
All of these benefits translate into three specific areas in which you can function at a more competitive level in the marketplace:

• More efficient implementation:
  algorithmic synthesis tools ensure that your product will give better performance, power and area results, with increased functionality.
• Get to market earlier:
  improved efficiency in the workplace will get your product to market more quickly, so that you can reap the advantages of higher prices and/or a larger market share.
• Share IP with other groups:
  by deploying algorithmic synthesis to work at a more abstract level, you can re-use your IP across multiple markets for further efficiency and cost-saving.

Conclusion
To be competitive in tomorrow's market, IC designers must find a solution to increasing costs and future complexity. The proven answer is to work at a higher level of abstraction by using algorithmic synthesis. Initial usage of algorithmic synthesis tools to build IC hardware has already demonstrated substantial time and cost benefits. The next stage is to deploy AS across your complete design for a more efficient and controllable IC creation process. As the basis of a high level flow, AS can make an even bigger contribution to your cycle reduction. Learning how to use and deploy algorithmic synthesis to work at a higher level of abstraction will greatly improve your ability to produce complex ICs on time and within budget, the two critical elements for competitive success.

About the Author:

Vinod Kathrail is the Chief Technical Officer at Synfora Inc.