Class T2
By implementing a chip-level bypass mechanism, Class T2 improves debugging performance for high chip-count applications by dramatically shortening the scan chain.

Since the TAP controllers in each chip are serially chained, prior to IEEE 1149.7, a design with many devices includes the TAP controller for each and every device in the scan chain. The example system in Figure 3 has three devices with five cores, contributing a total of 100 bits to the scan chain. If a developer wants to interrogate the last device on the chain he has to scan 100 bits each time. This can be quite inefficient, with the result that device access for embedded software developers is slower.

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The new chip-level bypass capability in IEEE 1149.7 freezes the TAP controller inside the devices that are not of interest and reduces the number of scan bits from 100 to eight (Figure 3). This decreases the number of bits needed to be shifted out of the system, dramatically improving the performance of the scan chain.

This mechanism can also function as a firewall. A firewall is useful for hot-connections to a target board while it's in operation. In IEEE 1149.1 systems, connecting to a running target may result in unpredictable operation, possibly caused by electrical issues resulting from the connection that may confuse the debug logic. With the bypass mechanism operating as a firewall, access to chip TAP is possible only after a predetermined sequence is initiated. This step ensures that a debug test system will connect only after a target has a stable electrical connection.

Class T3
Through the use of chip-select mechanisms and link-ID assignments, Class T3 allows developers to create star configuration instead of the traditional serial configuration of the IEEE 1149.1 standard. T3 implements a Star-4 or Wide Star as illustrated in Figure 4.

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In order to create a star configuration, the chips involved must be numbered. On start up, however, they do not have a number registered with the controller. Class T3 defines a method in which they are assigned numbers, essentially though a process of elimination based on their IDCODE and unique ID.

Class T3 creates a star configuration that enables the significant innovation of two-pin operation, which is implemented in Class T4. It should also be noted that upon power-up an IEEE 1149.7 system is compatible with IEEE 1149.1. By configuring the IEEE 1149.7 logic through ZBS, the advanced capabilities of IEEE 1149.7 become available.