Image capture and processing challenges--and solutions--in portable designs--Part II
Here is Part II of a four-part article series looking at the trends and design challenges of image acquisition and processing on cell phones and other hand-held platforms. This segment discusses wafer-level architecture.
By Giles Humpston, Tessera
Mobile Handset DesignLine
(09/22/08, 08:33:00 AM EDT)
Part I

The first part of this article series identified the primary drivers for the on-going development of camera modules. For the consumer, the driver is a better quality picture from single click 'point-and-shoot' operation. The handset manufacturer is more interested in reduced cost and height, as thin, portable electronics products is currently the fashion. However, the existing evolutionary roadmap of smaller and cheaper camera modules, without degraded picture quality, has come to an end. Achieving a step-wise reduction in cost and height, while simultaneously boosting optical performance, requires a radical new approach to camera module architecture, materials choices and assembly techniques.

Obsolescence of Discrete Assembly
Manufacture of a conventional camera module involves serial assembly from discrete parts. This has several fundamental limitations. First, the costs of assembly increase with every part manufactured. Once a high-volume line has been established, further gains in productivity can only be realized by diluting the administrative overhead for the facility by installing a parallel line with all the attendant capital costs involved.

Second, the precision of assembly increases with the quality of the image required. Image quality and imager resolution are linked, so manufacturing a megapixel camera module generally requires far greater mechanical precision than one of VGA resolution. The specifications of camera module assembly are already far more exacting than for conventional electronic components, necessitating more expensive machines, and generally compounded by slower throughput.

Third, each component must be manufacturable at the lowest possible cost. This means, for example, lenses must be radially symmetrical about the optical axis because this is the least expensive shape to produce and is compatible with using a screw thread mechanism to set camera focus. Imager die, however, always have a rectangular format, so there is clearly a mismatch between the aspect ratio of the lens train and the imager, which usually manifests as reduced image quality in the picture corners.

Finally, there are the consequences arising from the inability to make the product right the first time. While it is possible to set the optical axis of the lens train sufficiently close to that of the imager so as to not require adjustment, the same is not true of its height. The multiple glue line thicknesses and other variables can not be controlled with sufficient accuracy to fix the lens turret in position during manufacture. This means that every camera module must be placed in a test fixture, powered up and a series of images acquired while the focus is adjusted and then set. Clearly, this is a slow undertaking requiring a known good die tester equipped with an optical head, making final set-up of conventional camera modules a significant and unavoidable contributor to the manufacturing cost.

Wafer-Level Packaging
Wafer-level packaging of imagers is not a new architecture for camera modules, but, as it will be explained, it continues to enable design advancements.

The original basis of the move to wafer-level packaging of imagers was the need to decrease cost. While the adoption of wafer-level packaging actually increases assembly costs, it helps eliminate the major cause of yield loss from camera module manufacturing--particle contamination of, or damage to, the optically sensitive area of the imager. The benefit comes from attaching a cover glass to the face of the image sensor wafer as the very first process step (Figure 4). From that point on, the imager is totally protected from environmental and mechanical damage so the vast majority of good optical die on the wafer can be converted into yielded camera modules. (An imager die housed in a modern wafer-level package is shown in Figure 3 of Part 1 of this article series.)


A wafer-level package can be provided with a ball grid array interface on its rear surface. This allows the imager to be placed, with other components, on a common printed circuit board and attached by a single reflow soldering cycle, further minimizing assembly cost. The reliability of a ball grid array interface is also superior to the flexible circuit and connector of a conventional camera module built using chip-on-board assembly.

The wafer-level package must provide connectivity between the bond pads on the front face of the imager die and the ball grid array interface on the rear face of the package. There are a number of means by which this may be accomplished, and one has gained commercial acceptance in the form o a family of imager package solutions. More than 1 billion imagers have been included in these wafer-level packages since the technology was introduced in 2001. Not only will the packages pass the specification for cell phone parts with ease, they also exhibit a margin of safety of more than two over the more arduous JEDEC Level-1 automotive reliability standard.

Wafer-level packaging fails to be a low-cost solution if the materials and equipment set are derived from standard semiconductor practice. To achieve substantial cost reduction requires innovation in both of these areas. One approach that has proved highly successful is the adoption of mature materials produced in extremely high tonnage for an entirely different industry and purpose, and a tool set developed for the PCB industry [Humpston, G, et al., IEEE Trans. Advanced Packaging, 2008, 31(1), 33-38]. By this means, the packaging cost per die, including depreciation of the equipment, works out to a few cents per die, which is two orders of magnitude cheaper than discrete packaging.

Wafer-Level Optics
The cost reduction achieved from wafer-level packaging of the imager is beneficial, but does nothing to address the cost of the optical train or alter the height of the camera module. That requires an alternative approach to discrete optical assembly.

Much of the revolution that took place in the electronics industry in the 20th century is due to the innovation of the integrated circuit when discrete devices were replaced with an entirely new method wherein multiple devices are fabricated in close proximity while remaining individual entities. The 21st century may see a similar revolution by applying integration techniques to optics. Like integrated semiconductors, integrated optics can deliver substantial economies of scale, consistency of reproducibility and performance, and new functionality that can not be obtained from discrete optics. An example of this is the ability of diffractive optic elements to distribute light over a very wide space and/or in a precisely defined pattern at very high efficiency. The challenge is whether wafer-level optics can be used to reduce the cost and form factor of camera modules and, ideally, improve performance at the same time.

Wafer-scale packaging of imagers is economically attractive because the fixed process costs are divided among the number of good parts on the wafer. The same argument holds for manufacturing lenses at the wafer scale. By using several wafers of lenses, these can be easily and accurately stacked and bonded together. These stacks can then be singulated. The net result is an optical part with the same functionality as a conventional camera optic, but with greatly reduced costs and very precise and reproducible alignment.

Switching to wafer-scale manufacturing techniques provides new freedoms in materials choice and lens shape. The materials used to make wafer-scale lenses can have a higher refractive index than injection-molded lenses, whereby aiding size reduction. The materials chosen for the construction of the lenses can be selected for high temperature durability, facilitating surface mounting of the camera module and accompanying cost benefits. The precision of layer-to-layer and rotational alignment made possible by wafer-scale manufacturing means the lenses can have re-entrant profiles, diffractive surface features and be asymmetric in shape to match the rectangular format of the imager. These advances in optics permit the lens stack to be reduced in height without sacrificing optical performance.

Wafer-Level Camera Modules
While wafer-level packaging of imager die was originally developed as a means to decrease the cost of camera modules (by eliminating assembly yield loss) a highly fortuitous result is that the cover glass provides an exceptionally uniform surface, spaced an exact distance from the imager die. It therefore makes an ideal substrate or platform onto which a wafer-level optical stack can be attached. Owing to the high precision of the wafer-level imager package and also the wafer-level lens stack, they can be permanently joined without the need for costly, live adjustment of focus. The absence of moving parts and small size makes for an extremely robust product. Because the wafer-level stack has a considerably lower profile than the housing and lens turret it replaces, the resultant wafer-level camera module is appreciably smaller. This is clearly evident in Figure 5, which shows a VGA wafer-level camera with a camera module built from discrete parts. The wafer-level camera is 30 to 50 percent less expensive, has a form factor 50 percent smaller and is surface mountable.


Innovation in imager and optics wafer-level packaging has lead to the development of extremely compact camera modules that can be manufactured at low cost. However, these developments have not significantly altered the optical performance of the camera module. The means by which this can be accomplished are discussed in Part 3 of this article series.

About the Author
Giles Humpston, Ph.D., serves as Director, Research and Development of Tessera. Dr. Humpston has spent his entire professional career working in the field of semiconductor packaging, initially for military applications and more recently for high volume consumer products. He is a metallurgist by profession and has a doctorate in alloy phase equilibria. Dr. Humpston is a cited inventor on more than 75 patents and has co-authored several textbooks on metallic joining processes. His work and technical publications have been recognized by five international awards. Dr. Humpston's current interests are packaging of solid state camera modules and product miniaturization through wafer level technologies.