Today's intelligent system management designs in typical telecommunications or industrial control applications need to constantly monitor several voltage rails and take appropriate action when a certain condition exists. If a high-end telecommunications system must be shut down, for example, it is important that accuracy be very high and the output measurements are carefully calibrated to eliminate errors that can occur in the measurement process. For this reason, these applications need accuracy levels better than 1 percent. However, the total system accuracy offered by most analog-to-digital converters (ADC) signal chains may not sufficient.

In principle, the operation of an ADC is very simple. Given an analog input, it provides an accurate output value in digital format. However, in reality, the accuracy of the output voltage is subject to a number of factors, including gain and offset errors from the ADC and from other components in the signal chain.

Multiple discrete components, such as a pre-scaler or a divider network, have traditionally been used for calibration, to achieve the stringent accuracy and precision levels required by intelligent system management and industrial control applications. An alternate scenario is the use of a feature-rich, mixed-signal field-programmable gate array (FPGA) capable of supporting a calibration scheme, both in software and without the use of external components, to enable easier design implementation, improve accuracy, lower overall power consumption and increase signal integrity.

Calibration with ADCs and discrete devices
Calibration eliminates certain errors common to ADCs, such as offset and gain errors. Offset error, or "zero-scale" error, is the deviation from the minimum voltage expected when the minimum code is applied. For an ADC, the offset voltage is applied to the analog input and is increased until the first transition occurs.

On the other hand, gain error is the deviation in the slope of the transfer function when the offset error is removed from the ideal. Gain errors can be calibrated out with hardware or in software. However, if these errors are not adjusted, the measurements would be inaccurate and could impact the overall system performance.

As a result, calibration is an on-going exercise. Certain external factors, such as noise and drift over time, can introduce errors that affect measurements and, consequently, lower accuracy. By adjusting the offset and gain errors every so often, the accuracy of the ADC can be maintained.

Full-scale, or total channel, error is the sum of offset and gain errors. It is the error in the actual full-scale output transition point from the ideal value. Often, designers focus on the elimination of the full-scale error at the output of the ADC to provide better accuracy. Some ADCs offer internal trimming registers that allow the users to calibrate out the full-scale error. However, when the ADC does not support this feature, a combination hardware-software solution must be designed to resolve this situation.

Every time a measurement is done with the ADC, multiple discrete components, such as a microcontroller or digital-signal processor (DSP), are used for calibration. A common scheme calls for at least three components : a microcontroller or DSP, an EEPROM or flash memory device, and the ADC itself. In this scheme, the external flash memory device is used to store the offset error. The microcontroller or small DSP is used to compute the gain error and the actual value.

A one-point calibration scheme is commonly used to eliminate offset errors. A constant correction is applied to the measured data that would provide the corrected data. Even though this method is simple, it does not address gain errors.

Alternatively, a two-point calibration scheme measures the gain coefficients at two points, often at 20 percent and 80 percent of the full-range, along a straight-line fit. The fit is computed using Y=mx + c, where m is the gain error that is the slope of the straight line and c is the offset error, x is the measured value and Y is the corrected value. If the m and c coefficients are stored in memory and retrieved by software to compute the correction for each measurement, they can be used to eliminate the gain and offset errors to achieve higher overall accuracy.

This multiple-chip, hardware-software calibration approach has several tradeoffs. These discrete solutions can offer high levels of accuracy, but lack features and do not offer an expansion path. Further, discrete solutions may offer a specific input voltage range with a single polarity or limited number of input channels, forcing the designer to use multiple components to realize his design goals.

Multiple chips increase power consumption, noise, and cost, as well as add complexity to the overall system design. Other factors to be considered include the additional board space required to accommodate the discrete components; the design resources needed to ensure compatibility between the different components; and the signal integrity issues that result from the introduction of additional components on the board.

On the other hand, when higher performance is required, it is easy to replace individual components. For example, when a high-end telecommunications system or an industrial control application is being designed, a different ADC may be targeted, requiring only the replacement of the ADC, not the redesign of the entire calibration scheme.

Calibration with mixed-signal FPGAs
For designers looking to minimize the use of external components, a highly integrated mixed-signal FPGA solution offers all the essential features required to implement calibration for higher accuracy.

Today's mixed-signal FPGAs include embedded flash and SRAM blocks, FPGA logic, and analog functions, such as real-time clock (RTC), ADCs, FET gate driver output, and current, voltage and temperature monitoring blocks. These highly integrated programmable solutions, such as the Actel Fusion FPGA, also support the use of a variety of industry-standard processor cores, such as 8051 and ARM, making them compelling for system management, intelligent power management and embedded control applications.

One of the blocks within the FPGA is a pre-scaler circuit that can be used in conjunction with the ADC for monitoring voltage and temperature functions, for example. In a real-time monitoring application, the function being monitored may not provide a measurement within the required accuracy. As a result, a pre-scaler range needs to be selected to provide the best accuracy. Each pre-scaler has multiple scaling factors programmed by FPGA signals to support a large range of analog inputs with positive or negative polarity. The pre-scaler circuit scales the voltage applied to the ADC input pad such that it is compatible with the ADC input voltage range.

When the voltage being monitored is small compared to the chosen pre-scaler range, the accuracy may not be as good as a smaller range that is closer to the voltage being monitored. For example, when monitoring 3.3 V, the choice of pre-scaler range defines the accuracy that be achieved. Choosing a 16 V or 8 V range will not deliver accuracy levels as high as using the 4 V pre-scaler range.

The choice of the pre-scaler range plays a critical role in defining the accuracy that a customer can expect for his application. Similarly, if the reference voltage (V_ref) of the ADC is selected to be 2.56 V, for example, it is recommended that no pre-scalers be used and the direct input to the ADC be used instead, which can deliver much higher accuracy than with pre-scalers, making calibration unnecessary.

Generally, mixed-signal FPGAs are designed to a specific accuracy target, but an additional calibration option may be in place for customers who require higher accuracy levels. A software-based calibration option utilizes eNVM or flash memory blocks to store offset and gain coefficients; a calibration intellectual property (IP) core made of logic gates to implement the calibration solution; and SRAM memory blocks to process the data.

Combined with the integration benefits offered by devices such as mixed-signal Fusion FPGAs, the easy-to-use calibration option offers customers greater accuracy, lower system power, reduced design complexity, flexibility and more features than those offered by most discrete solutions.

During manufacturing testing, the offset and gain coefficients are pre-loaded and stored in the device. Therefore, upon receipt of the device, if the customer chooses to further calibrate the unit, the calibration IP engine retrieves the coefficients, computes the 'm' and 'c' for every measurement and applies the appropriate correction. The design flow is completely supported within the FPGA design flow, requiring the customer to have no prior calibration experience. Overall, the easy-to-use software-based calibration option enables customers to achieve better signal integrity and overall noise reduction.

An additional advantage of this FPGA's built-in calibration support is the ability to calibrate the device in the field. Boards exposed to differing environments over time can accumulate noise and the readings can drift. Generally, these boards and devices need to be calibrated to mitigate some of these noise issues.

With the Fusion FPGA, for example, the new updated offset and error coefficients are measured and stored in the flash memory. The customer can then use the calibration IP within the design flow to apply the updated corrections to the measured data. Alternatively, if a customer were to attempt to recalibrate a discrete component in the field, this may involve measurements in the field and recalibrating the unit using external components, adding to the overall system cost without providing an easy option for upgrade.

An example: calibration can provide the desired result
Customers who choose to use the calibration option in the mixed-signal FPGA can obtain very compelling results. Table 1 highlights accuracy levels without calibration (upper) and with calibration using the two-point 20-80% calibration scheme (lower).

Table 1: Accuracy levels without (upper) and with (lower) two-point calibration scheme

As demonstrated above, with the selection of an appropriate pre-scaler range for a specific, monitored voltage and the correct calibration option, customers can obtain accuracy better than 1 percent. This high level of accuracy will go a long way to mitigate general board-level noise issues.

Conclusion
To meet the very high accuracy levels required by many of today's intelligent system management designs, discrete solutions can offer high levels of accuracy and can be quickly replaced when the performance requirements or design specifications change. However, a multiple-chip scheme increases power consumption, noise and cost. Further, these solutions often lack features and do not offer an expansion path. Further, discrete solutions may offer a specific input voltage range with a single polarity or limited number of input channels, forcing the designer to use multiple components to realize his design goals.

To meet the required accuracy, a highly integrated FPGA with an easy-to-use, built-in, software-based calibration option enables customers to achieve overall noise reduction and accuracy better than 1 percent. Overall, combined with the integration benefits offered by mixed-signal FPGAs, the easy-to-use calibration option offers customers greater accuracy, lower system power, reduced design complexity, flexibility and more features than those offered by most discrete solutions.

About the author
Christian Plante is marketing director for the Fusion product line at Actel Corp., Mountain View, CA, www.actel.com