Since femtocells are targeted for individuals instead of group of communities, the users experience more dedicated wireless infrastructure with good signal strength for all of their mobile devices. In terms of data processing, both macro and femtocells will have more or less the same modules/complexity. However, femtocells design should be affordable as these are defined for individuals instead of communities. Therefore, usage of multiple costly processing devices in the femtocell design is not an option. Although we do not explain the details of full femtocell architecture in this paper, we will discuss the turbo coding of 3G standard² used for error correction capability of wireless network by keeping in mind the femtocell design budget requirements.

Implementing a 3G turbo encoder
The turbo encoder basically contains two constituent encoders separated by an interleaver. The schematic block diagram of 3G turbo recursive systematic code (RSC) encoder is shown in Figure 1. Each RSC encoder contains a forward path with a transfer function (1+D+D³) and a feedback path with a transfer function (1+D²+D³). The process of interleave address generation for each input is described in a paper from the 3rd Generation Partnership Project.² Unless we have many compute units, computing an interleave address on the fly is not an option with two MAC (multiply accumulate) units DSP such as Blackfin.

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Usually we precompute the interleave addresses and store them in a memory. The stored interleave addresses can be used for both turbo encoding and decoding. If codeword size is big, then we store precomputed interleaver addresses in L3 memory else we store them in L1 memory. In case of larger codewords, we use the window method to encode or decode the bits and use direct memory access to transfer data (such as inputs and interleave addresses) as needed from L3.

From Figure 1, for each input, we output one systematic bit X_i and two parity bits Y_i and Z_i. Here, parity bit Z_i doesn't depend directly on actual input bit bi but it depends on the bit b'_i which is from the interleaver buffer at index i. Given the input message block B of N bits, we either perform address computation to get interleaved bit b'_i from block B for each input bit index or we perform interleaving of total block B at once and store in as an interleaved block B' and access b'_i linearly with index i. Note that the computation of interleaved bit address according to 3G standard is not a simple task, and, therefore, we prefer to precompute the addresses and store them in a memory once for all N bits before start of encoding of multiple message data blocks. In this way we can ignore the complexity of the interleaver address generation of the turbo coding.