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Turbo encoders boost efficiency of a femtocell's DSP
With an efficient turbo-encoder algorithm, a multichannel 14.4-Mbps femtocell base station can be done on a single digital signal processor.



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After computing the encoded bits, we have to pack the encoded bits. As we're encoding four bits at a time and outputting an encoded 4-bit nibble at a time, packing nibbles into bytes is easy. We pack two nibbles into a byte in two cycles (with one left shift and one OR or ADD operation). For two encoder outputs packing, we spend four cycles on Blackfin. By using multiply-accumulate (MAC) unit, we can do this packing in two cycles for two encoders as we have two MAC units on the Blackfin. The Blackfin ASM code for encoding and packing of turbo encoder for single iteration of loop is shown in Listing 2. The ASM code of Listing 2 includes encoding and packing for both RSC encoders. It's clear from the ASM code that the turbo encoding of one byte consumes 20 cycles or 2.5 cycles per bit.

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In Listing 2, with the ASM code, we're encoding four bits at a time for two encoders. But, in reality the second encoder doesn't get the data directly from input bit-stream bytes. We have to interleave the input bit-stream before passing to the second encoder. We've already discussed the interleaving for second encoder, and we stored the interleaved bits in an interleaver buffer. There we assumed that the stored interleaved bits are accessed directly from the buffer for encoding by storing the interleaved bits in an addressable boundary (in other words, minimum of byte has to be used for storing one bit). Since, we're encoding in terms of nibbles using look-up table approach, we have to pack the interleaved bits back to bytes before storing them to the interleaver buffer.

Interleaver design. Because the look-up-table-based encoding method we just described needs the interleaved bits in byte form, we have to pack the interleaved bits to bytes. Therefore, to feed the bits to the second encoder in the right order, we have to perform the following three steps: unpack, interleave, and pack. As we represent the data in terms of bytes, packing and unpacking involve de-multiplexing and multiplexing of bytes into bits and bits into bytes respectively. Packing of bits to bytes need all interleaved bits, we have to perform interleaving first completely. The two operations (unpacking and interleaving) consume about three cycles per bit as shown in Listing 3. The ASM code shown in Listing 3 performs unpacking and interleaving of one byte of input data. An instruction rotate through carry rot r by -1 provides an unpacked data bit from end with the most significant bit (MSB).

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The next step is packing of interleaved data bits into bytes. The operation of packing is exactly reverse of unpacking operation shown in Listing 3. But, if we use rotate through carry instruction rot r by 1 for packing, we need two cycles per bit as we spend one cycle to move a data bit from a register to cc. Instead of rotate, we use compare and select vit_max instruction for packing purpose. The vit_max instruction packs two bits at a time by comparing the two least-significant-bit (LSB) words present in two registers with two MSB words of the same register. As the output flag of the comparison result of vit_max instruction is saved to accumulator, we extract the packed byte from the accumulator after four iterations. As we can not load two bits from the same buffer in one cycle to feed to vit_max instruction, we have to spend one more cycle to load the data bit. With this, we take two cycles to pack two bits or one cycle per bit as shown in Listing 4.

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