Understand the design implications of JESD204A for high-speed analog/digital and digital/analog converters (ADCs and DACs)
Editor's note: we are pleased to present this multipart in-depth technical article on JEDEC JESD204A, as well as design considerations when using this standard. This interface standard will have wide application with ADCs and DACs used in high-speed, wideband applications such as digital radio and telecom, usually in conjunction with FPGAs. While the standard is in some ways much more complex than existing interface approaches, it also greatly simplifies design, board layout, BOM, cost, PCB footprint, noise and EMI factors, and more.
The article is presented with an abstract and overview immediately below, followed by three detailed parts:
- Part 1: Serialization, Physical Layer, and Transport Layer
- Part 2: Data Framing, Interface Modes, and Scrambling and Test Mode will be posted a few days after Part 1
- Part 3: Data Link Layer, 8B/10B Encoding, Synchronization and Alignment, Lane Alignment, and Scalability and Performance will be posted a few days after Part 2
Abstract and overview
In 2008, JEDEC released a revision to the 2006 JESD204 data converter interface specification called (not surprisingly) JEDEC JESD204A. The "A" version of the specification addresses some key shortcomings of the original standard. Among these enhancements is the support for multiple data converters on multiple 3.125 Gbps data lanes, and embedded protocol support for the precise sample time-alignment of these multiple data lanes.
These enhancements should make a significant impact on the industry adoption of this standard. The multiple lane support means that there is no arbitrary limit to the data converter sample rate bandwidth (previously, the bandwidth was limited to 312.5 MB/sec) because multiple data lanes can be assigned to each DAC and ADC channel in JESD204A.
Equally important, the lane alignment in JESD204A means this standard is now relevant to communication system engineers. The lane alignment feature means that JESD204A data converters support phase-coherent quadrature sampling, which fundamental for the OFDM-based signal processing at the heart of wireless communications standards including LTE and WiMAX.
JEDEC JESD204A allows data converter manufacturers to greatly reduce the number of interconnect wires to the logic device with which they communicate. A dual-channel 14-bit ADC with a JESD204A interface has 80% fewer interconnect wires than a dual-channel 14-bit ADC with a conventional low-voltage CMOS parallel interface.
This device pin-count reduction enables BOM cost savings. Because plastic molding compound, bond wires, and lead frames have costs related to commodity prices, and are not subject to the economics of Moore's Law, packaging costs are becoming a higher and higher percentage of overall IC cost structures. JESD204A substitutes high-speed serial transceivers implemented in silicon, subject to Moore's Law, for lower bandwidth parallel I/O pins. Even over a short time horizon, this is a winning strategy for data converter vendors and customers, as the inexorable march of silicon economics plays out.
The fully expressed vision of JESD204A data acquisition systems includes guaranteed interoperability with FPGAs that possess the required SERDES -based transceivers. So long as design engineers follow the straightforward terminated transmission line PCB design rules outlined in the specification, they can expect smooth interworking of JESD204A-compliant data converters and FPGAs, bringing a new level of ease-of-use to high-speed data acquisition system design.
Finally, once the threshold "cost of entry" has been paid in terms of adding embedded state-machine based transceivers to data converters, the sky is the limit in terms of potential embedded "smarts". For example, JESD204A includes optional data scrambling to de-correlate any data-stream periodicity related to the analog signal being sampled or reconstructed. The standard also supports single-bit error detection, a feature well beyond the scope of conventional interfaces.
Collectively, these features have virtually no recurring marginal cost when implemented in a deep submicron process technology. One can easily imagine proprietary features added to the baseline JEDEC standard for simple digital filtering (such as high-pass dc blocking), peak detection and limiting, and other simple DSP functions.
In short, it appears the combined merits of time-aligned high-speed serial signaling, seamless FPGA interoperability, and intelligent bit handling are compelling enough to assure a permanent place for JEDEC JESD204A in the high-speed data converter universe.
About the author
Maury Wood, NXP High Speed Data Converter Marketing Manager, works with the Analog Mixed-Signal Business Line in Caen, Normandy, France.
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