With its new SH7786, Renesas has introduced a new concept in modular multimedia processors and complete multimedia system solutions for the automotive industry. Single-chip and System-on-Chip (SoC) processors provide customers with scalable and integrated solutions within a single product family. The new range offers a multi-core and multi-IP design for increased scalability, a key consideration during software development. Renesas' goal with the new range is to keep customers' development cycles as short as possible while increasing performance with each new generation. This evolutionary approach, based on current architectures, ensures low-risk system integration. The established SH superscalar architecture has not been abandoned, but rather complemented and extended with a dual-core processor.

The SH7786 is the first dual-core processor in the SH4A family's CPU range and will be followed this year by a dual-core SOC, an evolution of the SH7775. Renesas Technology made an early decision to adopt multi-core technology and developed a prototype chip with four SH-4A CPU cores and maximum processing power of 4,320 MIPS at a clock frequency of 600 MHz.

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A further prototype chip from Renesas Technology comprises eight SH-4A CPU cores. This chip achieves maximum processing power of 8,640 MIPS running at a clock frequency of 600 MHz and utilises low-power technology for multi-core LSIs.

The SH7786, a processor for the automotive sector with multi-core and multi-IP architecture, was based on the quad core technology chip RP1. In this case, Renesas moved from a higher to a lower level of integration.

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The SH7786 dual-core processor with 65nm process technology is especially suited to high-performance car multimedia systems and can achieve processing performance of up to 1,920 MIPS (960 MIPSx2 at 533MHz). The kernels can be coupled as symmetrical or asymmetrical multiprocessors (SMP/AMP). The CPU will be implemented in multimedia and 3D navigation systems as well as in sophisticated automotive applications. Along with the CPU kernels, the processor also features the integration of key standard interfaces for memory and speed. The SH7786 includes several PCI Express bus interfaces with a data throughput of up to 800 MBit/s, as well as a 32-bit memory interface for high-speed DDR3 SDRAM. The development of systems that include USB is facilitated by the SH7786's host and function support for high-speed (480 Megabit/s) USB 2.0. A media access controller (MAC), compliant with the IEEE 802.3 standard, makes it easier to implement connections to a 10/100 Megabit/s Ethernet LAN. There are also three low-power modes for each of the CPU kernels: Sleep, Light Sleep and Module Standby.

The advantage here is that one CPU core can continue to operate at full speed while the other is set to a low-power mode. This enables a reduction in power consumption as well as a fast reaction to changes in the processor workload. Each CPU has an integrated floating point processor unit (FPU) with a clock frequency of 533 MHz. The FPUs can execute operations in single-precision as well as double-precision mode and provide single-precision performance of 7.46 GFLOPS (giga floating point operations per second). In addition, each kernel is equipped with an internal cache configured with a 32 KB associative 4-way command cache and a 32 KB 4-way data cache. The support for cache coherence provides accelerated software processing. Every CPU also has 8 KB RAM to enable high-speed instruction fetches as well as 16 KB RAM for fast data access. The exception handling routines can be stored in this RAM area, significantly improving real-time system performance.

Renesas has consistently pursued a strategy of integration, as fewer external components ensure lower power consumption. Integrated functionality also increases data throughput (the IP blocks are located directly on the SuperHyway bus within the processor). This bidirectional bus provides data transfer of up to 3.2GB/s with a 64bit width. It also supports split transactions, separate address/control and data phases, burst, multiple bus masters and out-of-order transactions.

This illustrates how a modular architecture for next-generation embedded multimedia systems has been accomplished. It supports the complex calculations and high data rates of today's car information systems (CIS, with multimedia, navigation, image recognition and connectivity). The architecture of the overall system is already implemented partly in the processor, partly in the SOC, and even in the SIP (solution-in-package), especially where a higher level of integration is required. For SIPs, the CPU or the SOC as well as various memories and FPGAs can be integrated on a single substrate. This has several advantages, notably a positive effect on the EMI, a reduction in design time for CPU and memory connections, and guaranteed memory availability.

Along with hardware, software plays an important role in multi-core and multi-IP solutions. Renesas has worked closely with leading operating system providers when designing the dual-core CPU architecture. A snoop controller is integrated for SMP and ensures the coherence of the CPUs' internal memory cache by handling cache update data exchange between the cores.

The development of special compilers followed a similar path. These support sequential programming, which is common today, as well as parallel operation on the new multi-core systems. The system accesses the CPU cores directly via the compilers. The cores can be turned off individually, run at varying frequencies, or used in different operating modes, helping to keep power consumption as low as possible.

Supported by the compiler, a sequential application program can be divided up into different APIs for data assignment, data transfer and power reduction control. The next step is to convert these tasks into parallel code for each core, so that they end up as an executable on the relevant cores.

The SH7786 is based on Renesas' EXREAL platform which supports the design of systems with distributed tasks. This includes the implementation of different operating systems on multiple domains and enables the optimal use of the software resources for each operating system.

It is also possible to execute different operating systems simultaneously on one chip, such as navigation, dashboard and driver assistance. Developments are evolving away from single-kingdom navigation to real multi-core/multi-IP systems suitable for use in the automotive industry.

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Renesas' next-generation technology chip RP2 (2x quad core) was launched at the Microprocessor Forum 2008 in the US. The company's multi-core and multi-IP technology knows no bounds, as existing automotive solutions can be upgraded with new developments. Multi-core processors and multi-cores used as a system-on-chip, standalone or scalable solution provide symmetrical multiprocessing (SMP) and asymmetrical multiprocessing (AMP). SMP is a multiprocessor computer architecture in which two or more identical CPU cores simultaneously execute the same operating system. AMP is an architecture where two or more identical CPU cores each execute a different operating system, or different instances of the same operating system, independently of one another.

Matthias Wenzel is Marketing Manager CIS CAS for Renesas Technology Europe GmbH