Understanding the effect of clock jitter on high-speed ADCs (Part 1 of 2)

Derek Redmayne & Alison Steer, Linear Technology Corp.

August 12, 2008

Derek Redmayne & Alison Steer, Linear Technology Corp.

Digitizing high-speed signals to a high resolution requires careful selection of a clock that will not compromise the sampling performance of the analog-to-digital converter (ADC). In this article, we'll give you a better understanding of clock jitter and how it affects the performance of the high-speed ADC.

As an example, we will highlight the latest high-performance ADC from Linear Technology, the 16-bit, 160 Msps LTC2209. This converter exhibits a signal-to-noise ratio (SNR) of 77.4 dB, with 100 dB spur free dynamic range (SFDR) throughout much of the baseband region.

Like most high-speed ADCs on the market today, the LTC2209 uses a sample-and-hold (S&H) circuit that essentially takes a snapshot of the ADC input at an instant in time. When the S&H switch is closed, the network at the input of the ADC is connected to the sample capacitor. At the instant the switch is opened, one-half clock cycle later, the voltage on the capacitor is recorded and held.

Variation in the time at which the switch is opened is known as aperture uncertainty, or jitter, and will result in an error voltage that is proportional to the magnitude of the jitter and the input-signal slew rate. In other words, the greater the input frequency and amplitude, the more susceptible you are to jitter on the clock source. Figure 1 demonstrates this relationship of slew rate being proportional to jitter.

Figure 1: Slew rate exacerbates the effects of clock jitter.
(Click on image to enlarge)

Describing a clock as "low jitter" has become almost meaningless. This is because it means different things to different interest groups. For a programmable logic vendor, 30 picoseconds, or even 50 psec, is considered low jitter. In contrast, high-performance ADCs need a clock with jitter under1 psec, depending on the input frequency.

More precisely, spectral power distribution of the sampled signal is the determining factor, as opposed to simply the highest frequency component, unless a full-scale signal at the upper end of the spectrum is expected. For a simplistic example, a uniform band of power from DC to 1 MHz is 6 dB less sensitive than a single tone, or a narrow band, with equivalent power at 1 MHz.

There are various contributors to jitter in any scenario, extending from the oscillator to any frequency dividers, clock buffers and any noise acquired due to coupling effects, in addition to the internal aperture jitter of the ADC itself.

The internal aperture jitter of the LTC2209 is 70 femtoseconds (fsec). For the level of performance exhibited by the LTC2209 and other members in Linear Technology's high-speed 16-bit family, 0.5 psec jitter (the best available from many oscillator vendor) may produce discernable compromise in SNR for some sampling scenarios. It is not the ADC but the sampling scenario that dictates the required jitter performance.

Any ADC that exhibits 77 dB SNR at 140 MHz input frequency would require the same jitter performance to achieve full data sheet SNR. It is the input frequency, not the clock frequency, which is the determining factor with respect to jitter performance. On the LTC2209, a clock that has 10 psec jitter would cause a loss of only about 0.7 dB SNR at an input frequency of 1 MHz. At 140 MHz, the SNR would degrade to 41.1dB.

Figure 2 demonstrates the effects of clock jitter on the SNR of the LTC2209 as a function of sampled input frequency, with a family of curves of increasing clock jitter ranging from a perfect clock to 100 psec of jitter. At 100 psec, the ADC SNR begins to degrade with input frequencies of only 200 kHz!

Figure 2: Jitter degradation of SNR as a function of input frequency.
(Click on image to enlarge)

The theoretical limit on SNR resulting from clock jitter is:

where f_in is the input frequency and σ is the jitter in root mean square (RMS) seconds.

The jitter-related noise power is proportional to the input power (dBFS). As the input level is raised or decreased, the noise component related to jitter changes accordingly, For example, if we have a -1 dBFS input signal at a 70 MHz IF, sampled by a clock with 1 psec jitter, we can expect an SNR of 68 dBFS. At -5 dBFS, the noise component related to jitter would drop 4 dB to an SNR of 72 dBFS.

To calculate the total SNR degradation, we add the jitter-noise power to the published SNR of the ADC,

(Click on image to enlarge)

Understanding clock oscillator jitter specifications
Clock oscillators are usually specified in terms of spectral density of phase noise in dBc/Hz. An oscillator output can be decomposed into an amplitude term with associated amplitude noise and a frequency term with associated phase noise:

The spectral density measurements assume the AM component ε(t) of the noise is negligible compared to the phase noise component φ(t). This is a reasonable assumption with any quality frequency source.

The spectral density denoted as L(f) is stated as the ratio of the single-sideband phase-noise power in a 1-Hz bandwidth at an offset frequency, also called the Fourier frequency, relative to the carrier power:

(Click on image to enlarge)
Jitter is the integral of spectral phase density with respect to frequency between two limits in frequency, and expressed in time:

(Click on image to enlarge)
The result is frequency independent.

Most oscillators that rate jitter are rated between 12 kHz and 20 MHz. This is due to historical reasons related to optical communications and is not applicable to most other practical cases. Performance may, in fact, fall apart beyond these limits, so take care not to be lured in without careful examination.

For many oscillators where close-in phase noise dominates, the lower limit has the most impact on the published figure. While this expression is convenient, as it yields a single number useful for calculation of ADC SNR degradation, it is not as informative as the spectral density.

For example, two oscillators having different spectral content may have the same jitter over the same integration limits but may not produce the same SNR. Elevated wideband noise may not produce a poor jitter spec, but will degrade SNR. Close-in phase noise causes the fundamental signal to spread into adjacent frequency bins of an FFT, thereby reducing dynamic range, whereas broadband phase noise will uniformly elevate the noise floor throughout the entire Nyquist zone, thus reducing the overall SNR performance of the ADC.

Jitter does not affect SFDR unless the clock also contains spurs. The lower frequency limit of integration should correspond to the frequency resolution of any manipulations of the sampled data as the size of an FFT increases, for example.

Figure 3 shows the effect of band-limited clock jitter related to phase modulation of two signals of similar amplitude, but of different frequencies. This illustrates the exaggerated effect of both random phase noise and phase modulation of the clock in the presence of higher input frequencies. The clock input of the ADC should be regarded as the local oscillator port of the ADC, not a digital control signal. Anything present on the clock, including wideband noise extending to GHz frequencies, will mix with the input signal.

Figure 3: Effect of band-limited clock jitter related to phase modulation of two signals of similar amplitude, but of different frequencies.
(Click on image to enlarge)

(Part 2 will look at how the application, not the ADC, determines the clock-jitter need; selecting an oscillator to drive high-speed ADCs; and clock sources and architectures. You can read it by clicking here.)

Conclusion
The impact of jitter on ADC performance is a function of input frequency (slew rate), not sample rate. The choice of clock source will be determined by the application. Don't always believe the clock-source vendors. Test your clock sources with your ADC evaluation board before it is too late.

Related articles

• "Added resistor preserves crystal oscillator's low output jitter," Dr. Gary Giust, PhaseLink Corp.
• "Understand analog/digital converter clock jitter--and why you should care," Bill Odom, Applications Engineer, National Semiconductor Corp.
• "Enhance circuit timing design with programmable clock generators," Lin Wu, Product Marketing Manager, Texas Instruments

About the authors
Derek Redmayne is a mixed-signal applications engineer, and Alison Steer is a product marketing manager, both at Linear Technology Corp, Milpitas, CA.