Understanding the effect of clock jitter on high-speed ADCs (Part 2 of 2)(You can read Part 1 here)
The application determines the needs, not the ADC
Applications which are receiving weak signals which are in close proximity to strong tones, such as.static reflections in Doppler ultrasound, radar, and RFID, are sensitive to close-in phase noise. Conversely, when digitizing a CCD output, jitter generally doesn't matter due to the low slew rate at the point in time at which sampling occurs. Video applications are also not very sensitive. For example, in HDTV the sample window is approximately 6400 psec (time per pixel).
High symbol-rate communications applications are generally not sensitive to close-in phase noise, and may not be overly sensitive to the effects of wideband phase noise. High crest-factor waveforms (WCDMA OFDM) with relatively even power distribution have a low RMS power level, and also require headroom, so will not elevate the noise floor as much as a full amplitude single tone. However, higher-order modulation types, such as QAM and M-nary phase modulation, are more susceptible to noise and have more narrow carrier-recovery loop bandwidths for the same symbol rates as, for example, QPSK used in CDMA systems.
A digital radio where strong interferers (single tones) may appear in close proximity, or may be much stronger than the signal of interest, is generally demanding in terms of close-in phase noise, and may be sensitive to wideband phase noise. As any wideband signal source tends to have a high crest factor, and requires headroom for interferers, the nominal power at the ADC may be low. The characteristics of the band of interest must be taken into consideration in deciding on a clock source.
Selecting an oscillator to drive high-speed ADCs
Most oscillators will have close-in phase noise that will limit the dynamic range close to a strong fundamental. If close-in phase noise is important, based on your dynamic range requirement in proximity to strong tones, you may need a phase locked loop (PLL) to reduce the close-in noise of your oscillator source, or to lock your oscillator to an accurate frequency reference. The use of a PLL as a jitter cleaner essentially provides a very narrowband tracking filter.
Your choice of oscillator will dictate your loop bandwidth, as well; your desired loop bandwidth will dictate the oscillator. A voltage-controlled crystal oscillator (VCXO) requires only a narrow loop bandwidth to track a stable reference. VCOs can provide wide tuning range, but need wider loop bandwidth in order to reduce their close-in phase noise to acceptable levels.
If you only require a very restricted tuning range, perhaps locking to a reference oscillator, the use of a VCXO is the best option. If you need the octave tuning range of a VCO, and need low close-in phase noise, you may have a problem, especially if you need high divider ratios and low reference-comparison frequencies in your PLL. Figure 4 shows a real VCXO phase noise plot, compared to a typical VCO.
Figure 4: Comparison of VCXO versus hypothetical VCO phase-noise performance
(Click on image to enlarge)
The optimal loop bandwidth for the PLL is suggested by the intersection of the noise density of the reference oscillator as multiplied by the center frequency, and the phase-noise plot of the VCXO or VCO. The example would suggest 2 kHz for the VCXO, and 300 kHz for the VCO. A 300 kHz corner requires a comparison frequency of at least 3 MHz, which suggests 5 MHz.
The VCXO could be used with a comparison frequency as low as 20 kHz. If a lower frequency reference were used (high divide ratios) with the VCO, the intersection of the multiplied phase noise with that of the VCO would be at a lower frequency, substantially increasing the jitter. The use of an excessively low loop bandwidth with a lower multiplication ratio will cause the phase noise of a VCO to remain within the loop bandwidth. If your application is insensitive to close-in phase noise, and does not need to be locked to a reference, an XO can be used.
Clock sources and clock architectures
A good clock can be compromised by routing it through an FPGA where internal crosstalk is prevalent. FPGAs often maximize their input/output connections (I/Os) at the expense of ground pins, resulting in ground bounce. If the FPGA is driving outputs at different rates, these will manifest themselves in any clock routed through the FPGA, and ultimately on the output of any ADC using that clock.
A low-noise flip-flop clocked by the clean VCO signal can be used as a retiming stage to eliminate jitter when an FPGA is used to frequency-divide the VCO. The FPGA can be used to implement a narrow-band PLL for an external VCXO, with an external loop filter, and a loop-filter driver protected from reflected ground bounce from the FPGA. Do not use a digital lock loop (DLL) to produce a clock for an ADC unless you are over-sampling the audio band.
A good clock can also be compromised by routing it among digital signals. Any clock originating at any distance from the ADC must be routed through a conduit of copper and vias. Figure 5 shows examples of good and bad routing of clocks. The bad cases are where the clocks are within cavities shared with digital signals.
Figure 5: Example of good and bad layout for clock routing.
(Click on image to enlarge)
The impact of jitter on ADC performance is a function of input frequency (slew rate), not sample rate. The choice of clock source will be determined by the application. Don't always believe the clock-source vendors. Test your clock sources with your ADC evaluation board before it is too late.
- "Added resistor preserves crystal oscillator's low output jitter," Dr. Gary Giust, PhaseLink Corp.
- "Understand analog/digital converter clock jitter--and why you should care," Bill Odom, Applications Engineer, National Semiconductor Corp.
- "Enhance circuit timing design with programmable clock generators," Lin Wu, Product Marketing Manager, Texas Instruments
About the authors
Derek Redmayne is a mixed-signal applications engineer, and Alison Steer is a product marketing manager, both at Linear Technology Corp, Milpitas, CA.