Tutorial: Improving the transient immunity of your microcontroller-based embedded design - Part 3The first and best opportunity to eliminate conducted transient immunity problems is at the point of power or signal entry into the application. If the immunity signal can be sufficiently suppressed at this point, the remaining hardware and software techniques are not necessary.
The impact of this is threefold: the risk on noncompliance is reduced or eliminated, less cost and effort will have to be expended in other areas of the design, and schedule delays due to transient immunity issues can be eliminated with a high probability.
Examples of point of entry power filters and signal line filters are shown in Figures 1a, 1b, and Figure 2, below, respectively. Power filters are readily available from numerous vendors in both standard and custom packages. Filter performance can also be selected from standard offerings or customized for the particular application.
|Fig. 1a. Standard point of entry power filters||Fig. 1b. Custom point of entry power filters|
While many prepackaged filter solutions exist, they are by no means necessary. Filters implemented with discrete components can easily achieve the necessary performance with more flexibility and potentially lower cost.
|Fig. 2. Point of entry signal line filter examples|
Even filters built manually on printed wiring boards (PWBs) are effective if located properly in the application. Any filter needs to be placed as close as possible to the power or signal point of entry into the application.
The primary consideration is to filter the undesired noise from the power or signal lines before it can either couple to other wires within the application or conduct onto the application PCB as shown in Figure 3, below.
|Figure 3. Point of entry filter placement|
If power and signal connections to the application are not optimized for transient suppression at the point of entry, the compliance problem increases in complexity because control of the immunity signals has been lost. The result is that all of the remaining hardware and software techniques may be needed to ensure good electromagnetic compatibility (EMC) performance.
System Connector Location
If power and signals are filtered at their point of entry into the application, the location of connectors is not critical. However, if the power and signals are not filtered, connector location becomes very important. In this case, connectors should be located so that the cable's length between the application chassis and the connected load is as short as possible.
A short connection will reduce the amount of energy radiated into the chassis but will have no effect on the conducted immunity signal. In addition, physically separate or isolate power connectors from signal connectors as much as possible.
System Cable Routing
Where cable lines are unfiltered, never, under any circumstances, route power lines and signal lines in the same cable bundle. Doing so will only ensure that the noise on the power/signal lines will be coupled to the other signal/power lines in the bundle. Failing to follow this rule will serve to maximize the complexity of the immunity problem by ensuring many more noisy signals to suppress in the system.
Where cable lines are filtered, power and signal lines may be routed together in the same cable bundle only if there is no possibility of creating a self-compatibility problem. For instance, a self-compatibility problem may exist if the application contains subsystems or components that generate transient noise as a result of normal operation (i.e. " relays, motors, compressors, etc.). If the possibility of a self-compatibility problem exists, default to the rule for unfiltered lines.
System Component Placement
The placement of subsystems, components or cables is important " particularly for self-compatibility. Noisy subsystems, components or cables should be physically isolated from sensitive electronics, such as the microcontroller (MCU), to minimize radiated noise coupling. Physical isolation can take the form of separation (distance) or shielding.
Bypassing is the reduction of high frequency current flow in a high impedance path by shunting that path with a bypass, typically a capacitor4. Bypassing is used to reduce current noise on power supply lines by reducing the time rate of change of current (di/dt) being drawn through the inductance of the power distribution system. A capacitor performs this function by providing a local source of high frequency current at the integrated circuit (IC).
Inadequate bypassing increases system noise margins and ultimately leads to incorrect, unreliable, or unstable operation. For a bypass network (a capacitor or group of capacitors) to perform properly, the following conditions are necessary:
1) The capacitance must be
sufficient to provide the needed transient current to the load,
2) The impedance between the network and its load must be very low, and
3) The loop area of the network must be as small as possible.
The size of the required capacitance can either be calculated using readily available formulas and the characteristics of the decoupled MCU or, even better, by experimentation and measurement. The following set of equations will give the designer a good starting point for selecting the correct decoupling capacitance. The equations and associated steps are as follows:
1. Determine the average power supply current (Iavg),This parameter can be measured or calculated from the MCU electrical specification by
where Pavg is the average power dissipated by the MCU, and VDD is the power supply voltage. The average power is typically referred to in Freescale electrical specifications as the dissipated power (PD), which consists of both internal core power (PINT) and input/output (I/O) pin power (PI/O) such that
PD can be calculated from the equations provided in an MCU electrical specification or measured. PI/O can also be calculated or measured but, in some applications, it can be neglected2. Calculate the charge (¾Q) to be drawn from the decoupling capacitor at the clock edge by
where fc is the clock frequency.
3. Calculate the capacitance (C) needed to source the needed charge while maintaining the voltage supply to within some ripple specification by
where n is the supply voltage ripple in percent (%).
4. Select a package with a resonant frequency (fo) that is at least twice the clock frequency by
where Lpackage is the series inductance on the selected package. This inductance is typically associated with the package leads and aspect ratio " shorter and wider leads will provide less inductance and a higher resonant frequency. The impedance of a capacitor over frequency (ZC(jw)) is calculated by
= 2 x x f
Decoupling is the isolation of two circuits on a common power supply to prevent the transmission of noise. The decoupling circuit is typically a low-pass filter. The low-pass filter is usually not symmetrical " the isolation is not equal in both directions though the network. Decoupling achieves circuit isolation by utilizing shunt elements (capacitors, TVS, etc.) and/or block elements (resistors, inductors, ferrites, etc.) to limit the high-frequency content of transmitted signals or power. Noise that is not shunted to its return path will be attenuated by the series impedance.
Bypassing and Decoupling Layout
To achieve optimal performance of the power distribution network, any shunt element connected between any of the MCU pins and VSS should be connected to the MCU VSS pin(s) using planes or short, wide traces.
The impedance of these connections and, therefore, the performance of the shunt element, can be adversely affected by the layout patterns used on the PCB to mount the component and connect it to the MCU. These layout patterns add series inductance to the impedance of the network resulting in a lower resonant frequency. A comparison of component layout patterns is shown in Figure 4, below.
|Figure 4. Layout pattern inductance comparison|
Reducing the impedance of the power distribution network can also be achieved by minimizing the loop area of the filter network. An example of filter network (decoupling capacitor) current loop area is shown in Figure 5, below.
As the length of the trace (x) between the MCU and decoupling capacitor increases, the loop and series inductance also increase. This reduces the efficiency of radiated emissions and susceptibility coupling.
|Figure 5. Decoupling loop area|
MCU Oscillator Circuit
Two types of clock sources are typically used for microcontroller-based applications: mechanical resonant devices such as crystals and ceramic resonators; and passive RC (resistor-capacitor) oscillators. The characteristics of these clock sources and other commonly used clock sources are described in Table 1, below.
The optimum clock source for a particular application will depend on cost, required accuracy, desired power consumption, and the requirements of the operational environment " which includes EMC.
|Table 1. Characteristics of Clock Sources (Source: Maxim application note AN2154 "Microcontroller Clock -Crystal, Resonator, RC Oscillator, or Silicon Oscillator?", 02 July 2003, http://www.maxim-ic.com.)|
Normal values of feedback resistor in an external oscillator circuit do not affect noise susceptibility. However, noise susceptibility (ability of spurious noise to disrupt the crystal) is affected when the series resistance is too high.
The choice of bias resistor and load capacitors in the oscillator circuit (in the case of the Pierce oscillator configuration) can lower the signal amplitude at the oscillator input pin (typically OSC1 or EXTAL) which increases the chance that input noise can disrupt the signal. In systems with electromagnetic susceptibility concerns, an oscillator configuration should be chosen which results in a large amplitude signal at the oscillator input pin.
In addition, lower frequency crystal oscillator circuits result in signals with slower rise and fall times and the oscillator input pin. This increases the potential of noise affecting the input signal.
The oscillator circuit is often a primary source of susceptibility in an application. To maximize immunity, the oscillator components should be closely grouped and located next to the oscillator pins of the MCU. All traces associated with the oscillator circuit should be as short as possible.
The oscillator circuit should be surrounded by guard traces connected to the VSS pin of the MCU with short ground traces or a ground plane. The oscillator circuitry should also be physically isolated or shielded from any I/O signal traces routed to off-board connectors.
Whether at the system or PCB level, transients on input signals create a particularly challenging problem. Inputs are typically coupled to supply and ground through electromagnetic interference (EMI) and electrostatic discharge (ESD) control devices in addition to being connected to circuitry that will operate on the state of the signal.
As a result, inputs require the same considerations as power pins but include additional considerations tied to the functional requirements of the application.
EMI and ESD control devices must provide the required level of protection without degrading the input signal or the characteristics of the receiving circuitry beyond specification. For circuitry with an operating bandwidth outside the noise bandwidth of the transient waveform, protection can be achieved by the use of low-pass, high-pass, or band-pass filters.
For circuitry with an operating bandwidth within the noise bandwidth of the transient waveform, implementing effective protection without, at least temporarily, degrading performance can be very difficult or even impossible. In this case, the designer may have to rely on software techniques discussed later.
The standard protection for inputs is the low-pass filter as shown in Figure 6, below. The series resistance limits the injected current. The parallel capacitor shunts the transient current into the ground system as it attempts to hold the voltage to its steady-state value. The values of resistance and capacitance can be varied to either maximize protection or minimize impact on the input signal. While typically referenced to VSS (as shown), the capacitor can also be referenced to VDD.
|Figure 6. Typical low-pass filter transient protection on input pin|
Additional strategies for limiting transients on inputs include:
1) Clamp the input voltage
transient voltage suppressor (TVS) devices.
2) Limit the input current using series resistance or impedance.
3) Shield input cables with braided or solid shields.
4) Shield PCB traces with guard traces, microstrip or stripline techniques.
5) Utilize line terminations to reduce ringing and overshoot.
6) Terminate unused input pins to VDD or VSS.
If sensitive input signals are to be routed off the PCB, place the MCU near the off-board connector. If not, place the MCU where the trace lengths of these signals will be as short as possible.Next in Part 4: PCB Power Supply and Floor Plan Opportunities
To read Part 1, go to: Defining the Problem
To read Part 2, go to: Hardware Techniques - The basic circuit building blocks
Ross Carlton has specialized in
all aspects of electromagnetic compatibility (EMC) since his graduation
from Texas A&M University with a Bachelor of Science in Electrical
Engineering in 1985. He has been with Freescale Semiconductor for the
last eight years where he has led the EMC design, test and support of
Freescale's 8, 16, and 32-bit microcontroller products. In addition,
Ross represents the U.S. as a Technical Expert to IEC
Subcommittee 47A on integrated circuits where he is the project leader
for IEC 61967-2, IEC 61967-3 and IEC 62132-2. He is currently involved in
developing transient immunity test methodologies for standardization.
The author would like to thank Greg Racino and John Suchyta, 8-Bit Applications Engineer at Freescale Semiconductor for their inputs and guidance. Their contributions were critical to ensuring consistent and correct guidance.
1. Ross Carlton, Greg Racino, John Suchyta, Improving the Transient Immunity Performance of Microcontroller-based applications. Freescale Application Note (AN) 2764).
61000-4-2, Electromagnetic compatibility (EMC) - Part 4-2: Testing and
measurement techniques - Electrostatic discharge immunity test, International
Electrotechnical Commission, 2001.
3. IEC 61000-4-4, Electromagnetic Compatibility (EMC) - Part 4-4: Testing and measurement techniques - Electrical fast transient/burst immunity test, International Electrotechnical Commission, 2001.
4. Ronald B. Standler, Protection of Electronic Circuits from Overvoltages, John Wiley & Sons, 1989, pp. 265-283.
5. Ken Kundert, "Power Supply Noise Reduction", The Designer's Guide , 2004.
6. Larry D. Smith, "Decoupling Capacitor Calculations for CMOS Circuits", Electrical Performance of Electrical Packages Conference, Monterey CA, November 1994, Pages 101-105.
7. Ronald B. Standler, Protection of Electronic Circuits from Overvoltages, John Wiley & Sons, 1989.
8. Clayton Paul, Introduction to Electromagnetic Compatibility, Wiley & Sons, 1992.
9. Bernard Keiser, Principles of Electromagnetic Compatibility, Artech House, 1987.
10. T.C. Lun, "Designing for Board Level Electromagnetic Compatibility", Motorola Application Note (AN) 2321.