Building an FPGA-based Digital Down Converter
This "Product How-To" article focuses how to use a certain product in an embedded system and is written by a company representative.
The digital downconverter (DDC) has become a cornerstone technology in communication systems. Similar to its analog receiver counterpart, the DDC provides the user with a means to tune and extract a frequency of interest from a broad radio spectrum.
Over the past few years, the functions associated with DDCs have seen a shift from being delivered in ASICs to operating as IP (intellectual property) in FPGAs.
For many applications, this implementation shift brings advantages such as design flexibility, higher precision processing, higher channel density, lower power and lower cost per channel. With the advent of each new higher performance FPGA family, these benefits continue to increase.
This article explores some of the key advantages of implementing DDC designs in FPGAs and describes some of the situations when ASICs can still offer the best solution.
To understand how FPGAs play a key role in implementing DDCs that perform the function of a receiver, it's important to break the DDC down into its individual functional blocks.
Figure 1 below shows a classic DDC. Whether it's implemented in an ASIC or an FPGA, this is the common architecture of the DDC function.
|Figure 1: Regardless of whether it's implemented in an ASIC or an FPGA, this is the common architecture of the DDC function.|
The first stage of the DDC uses a complex digital mixer to translate the frequency of interest down to baseband. It uses a pair of multipliers and a direct digital synthesizer as the numerically controlled oscillator.
This function enables the user to tune the receiver to the desired frequency of interest. The second stage of the DDC reduces the sampling frequency of the signal to match the desired output bandwidth. It uses a cascaded integrator comb (CIC) filter to decimate the data.
A second CIC filter provides a coarse gain adjustment stage. The signal is then passed to a pair of additional polyphase filters—first, a compensation FIR filter then a programmable FIR filter. This filter pair provides additional decimation and final signal shaping prior to the rounding stage and final output.
When we get past all the acronyms, we realize that most of the individual function blocks of the DDC are implemented using multipliers. Thus, it becomes apparent how the DDC might map into current FPGA families.
Most new FPGAs include a wealth of DSP function blocks that are primarily multipliers. The general purpose logic resource and onchip memory of FPGAs also match the requirements of the DDC for implementing the required FIR filters and filter coefficient tables.
DDCs as IP cores
As part of its IP library series, Xilinx provides a free DDC core. The core serves as a good general reference design, following the classic DDC architecture shown in Figure 1 above.
While this core can be used as a building block for general-purpose DDCs, the real advantages of an IP-based implementation can be best seen in optimized custom cores that are designed to match the requirements of a specific application.
Pentek offers a series of highperformance IP-based DDCs, available preinstalled in software radio modules. Each is optimized to match a specific range of application requirements. These cores range from the high-channel count/narrow bandwidth of the 430 Core installed in the Model 7141 to the wider bandwidths and excellent spurious free dynamic range (SFDR) of the core installed in the Model 7153.
Table 1 below lists the range of DDC cores available from Pentek as software radio modules. For each core, pertinent specifications are listed. All products are available in industry-standard PMC/XMC modules as well as 3U and 6U CompactPCI, PCI and PCIe form factors.
|Table 1: Listed are the performance characteristics of ASIC and FPGA IP DDC Cores.|
In addition to the IPbased solutions, a popular ASICbased DDC solution from Texas Instruments—the GC4016—is included as a reference. When compared on a size/ power/cost per channel basis, it becomes apparent that narrowband, high channel-count DDC cores can be very efficiently implemented in FPGAs. Implementation of wideband DDCs consumes many more FPGA DSP and logic resources.
As a result, the number of channels that can be fit into a single FPGA is limited. Even with less cost-effective wide-band DDCs, the custom IP approach can sometimes provide the only viable solution when a specific performance characteristic is required. The improved SFDR of the Pentek 420 core is an example of such a requirement.