Leveraging FPGA and CPLD digital logic to implement analog to digital converters
Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).
The ADC is a common analog building block and almost always is needed when interfacing digital logic, like that in an FPGA or CPLD, to the 'real world' of analog sensors. This article will explain the implementation of both a low frequency (DC to 1K Hz) and higher frequency (up to 50K Hz) ADC using reference designs and demo boards available from Lattice Semiconductor.
A sample application for each design: one for a system monitor in a network switch, and another for frequency detection in an audio communication system, will be examined.
Analog to digital converter implementation overview
A simple analog to digital converter can be constructed by adding a small RC circuit to an LVDS input on an FPGA or CPLD. As illustrated in the bottom left of figure 1, the RC network is placed on one side of the LVDS input and the Analog Input of interest is placed on the other side.
The LVDS input will act as a simple analog comparator and will output a digital '1' if the analog input voltage is higher than the voltage from the RC network. By changing the voltage on the input to the RC circuit (from the generic output of the FPGA/CPLD), the LVDS comparator can be used to analyze the analog input voltage to create an accurate digital representation.
The analog to digital control module can be implemented in a variety of ways, depending on the frequency of the Analog Input, the desired resolution and the logic resources available. A low frequency signal can be processed using a simple successive approximation register, as shown in option 1 at the top left of figure 1.
A higher frequency implementation, shown on the top right of figure 1, can be implemented using a delta sigma modulator function, which consists of a sampling register and a cascade integrated comb (CIC) filter.
Once the digital signal has been constructed, the digital output can be optionally filtered to remove any unwanted high frequency components introduced by system noise or feedback jitter (explained in more detail below).
After the optional digital filter block, an optional memory buffer can be used for debug/testing purposes. The digital output can be sampled by the memory buffer and then scanned out via a JTAG port into a personal computer running signal analysis software.
To see a bigger version of this graphic click here.
Fig 1: Analog to digital converter basic block diagram: low frequency and high frequency options
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