How to use an FPGA to test a PLL band calibration algorithm
It's a common technique to split the required frequency tuning range of a controlled oscillator into discrete bands. The advantage of having many bands is that a wide tuning range can be covered while keeping a relatively low voltage-controlled oscillator (VCO) gain within each band. Low VCO gain is good for achieving low VCO phase noise. It's required that the frequency bands overlap. The tuning bands are changed with a digital band control signal.
When an oscillator with discrete tuning bands is used in a phase-locked loop (PLL), the desired band must be selected before the PLL can proceed to phase lock. This necessary step has many names (band calibration, auto-band selection, band selection, and so on), but the idea is the same: to pick the right frequency band before allowing the PLL to lock.
A straightforward way to calibrate the band is by racing two counters, one clocked with the reference clock and the other clocked with the feedback clock that is the frequency divided version of the VCO output. The frequency division occurs in a block called a multi-modulus divider (MMD).
The counters are forced to start at the same time and permitted to count up to a predetermined value. Whichever counter gets to the value first is noted as the winner; it follows that that clock was greater in frequency.
Using the information about which counter was the winner, the band control of the VCO can be either incremented or decremented to bring the frequencies closer. This algorithm is implemented in a band calibration block (BCAL). Instead of waiting for an expensive ASIC fabrication run that includes the entire PLL and other circuits, you can implement a band calibration algorithm and test it on an FPGA. This article shows you how.
VCO band calibration (BCAL)
In communications chips, frequency synthesizers are ubiquitous functional blocks. A frequency synthesizer is loosely defined as a PLL that generates an output frequency that's directly proportional to a reference frequency. The constant of proportionality is a specific subset of integer or real numbers, depending on the synthesizer implementation.
One use for a synthesizer in a receiver front-end is the creation of the local oscillator input to a mixer that downconverts the received radio frequency (RF) signal to an intermediate frequency. Channel selection is achieved by setting the synthesizer's constant of proportionality. In general, RF = Ndiv * REF, where RF is the output frequency, Ndiv is the constant of proportionality, and REF is the reference frequency.
Ndiv can be a ratio of integers, N/R, where N is an integer divide value for the output of the VCO, and R is another integer divide ratio for dividing the reference oscillator. If even finer frequency resolution is needed, the N value can be added to a sigma-delta modulated code that dithers the divider function and gives a fractional resolution of REF/2^(# sigma-delta accumulator bits).
Frequency synthesizers multiply a fixed frequency crystal oscillator up to the required frequency. The PLL acts as a closed-loop negative feedback system to implement this exact multiplication. The job of the MMD is to divide the frequency of the VCO output by the integer value N.
The phase of this signal is compared with the phase of the reference, and the difference in phases is filtered to remove high-frequency components. The filtered signal is used as the voltage control of the VCO. If there is any phase difference between the output of the MMD and the reference, the control voltage at the VCO will adjust to correct that phase difference.
For the application at hand, the synthesizer needed to create frequencies from 3,000 to 4,000 MHz. Continuous tuning of the VCO is accomplished by changing the bias voltage across a varactor which is part of the parallel inductor-capacitor (LC) resonant circuit. The fabrication technology limits the control voltage to a maximum change of about 1.5 V. It's difficult to build a varactor that will change its reactance enough to cause a frequency change of 1,000 MHz with only a control voltage change of 1.5 V.
Furthermore, a large VCO gain of 1,000 MHz/1.5 V would make the PLL susceptible to high phase noise. For these reasons, the tuning range is split up into discrete bands. The discrete bands are implemented by adding binary-weighted capacitors to the parallel LC tank circuit. They are switched on or off depending on the digital band setting. The band must be set before the PLL can be allowed to lock and track in a continuous manner.
The BCAL circuit operates as a second feedback loop controlling the VCO through its band input. During band calibration, the VCO control voltage is fixed at a convenient voltage, usually the mid-point of its allowable control voltage range. The phase-detector is also disabled during band calibration.
My goal was to design and test the band calibration algorithm before integrating it with the PLL on an RF receiver ASIC. To that end, a system analogous to the PLL when it's being band-calibrated was constructed entirely with circuits that could be implemented on an FPGA. Since the VCO and MMD lumped together act as a programmable oscillator with output frequencies around the reference frequency, their functionality can be modeled by a numerically-controlled oscillator (NCO), shown in Figure 1.
 Click on image to enlarge. |
For the synthesizer to have low phase noise, a crystal generates the frequency reference. The reference frequency is typically in the tens of MHz, which is well below the maximum speed of the logic that can be implemented on today's FPGAs. The BCAL algorithm itself can be described and designed with digital techniques.
At its simplest, its inputs are two clocks, the reference and the output of the NCO; its output is the band signal for the NCO. The combination of the band calibration, NCO, and an externally applied reference signal forms a closed loop system with negative feedback that is analogous to the PLL operating during its band calibration mode, all of which can be coded in RTL and tested on an FPGA before spending money on an ASIC fabrication.
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