Case study of PID control in an FPGA
FPGA architecture
The block diagram below illustrates the FPGA used for the PID control implementation. The functionality of this FPGA, in addition to the PID Controller, includes the following:
- Calibration calculations
- Moving average filter
- Waveform setpoint tables
- Waveform control
- PID state machine
Figure 2: FPGA PID Controller Block Diagram(To view larger image click here.)
The ADCs are 16-bit, 250 kSPS. The DAC is 14-bit, 250 kSPS.
Calibration calculations
One of the requirements of this product was high accuracy voltage and current measurements (± 5 mV and ± 5 mA). To achieve this accuracy, it was necessary to calibrate the electronic load circuitry, which had small non-linearities and an inherent offset. So the first calculation done on the data, after it was read from the ADCs, was to apply calibration parameters found previously using independent, external measurement equipment.
These calibration parameters are loaded into FPGA registers at power-up.
The calibration parameters were an offset and a gain. The voltage and current offset was simply the ADC value at 0 V or 0 A. The voltage and current gain represent the linearity of the load circuitry. These parameters are expressed by the following equations:
The electronic load hardware is relatively linear so the gain parameter is going to be close to unity. It was assumed, based on circuit analysis and results from the previous generation product, that the gain would never be larger than two. To add the most amount of precision possible to the gain using that assumption, the software loads a gain value in [1.15] fixed-point format.
After the gain is applied to the measurement, the result is rounded to the nearest whole ADC value, eliminating the decimal digits just introduced. From this point, all of the calculations in the loop are done in whole numbers. The remaining math in the control loop is done with whole numbers.
ADC0 is the ADC value for a 0 V or 0 A input. ADC1 is the ADC value for a given voltage or current input. The ideal values are the values that the ADC would output if it were perfectly linear. The ideal ADC value for a given input can be calculated from the following equations,
All of the above equations are used by the software to calculate the calibration parameters. The following equation is used by the FPGA to find the calibrated value, and it is illustrated in Figure 3 below.
Calibrated _ Value =(Raw _ Value - Offset ) ×Gain
Figure 3: Calibration Block Diagram (To view larger image click here.)
To further improve the accuracy of the measurements, different calibration parameters are selected depending on the value of the voltage and the current. For voltage calibration, there are 8 sets of calibration constants, each applying to a range of raw voltage readings as shown in Table 1 below:
Table 1: Calibration Parameter Ranges
For current calibration, there are 16 sets of calibration constants, with two groups of 8. Each of the two groups applies to the range of raw current readings similar to the voltage calibration
ranges. One group is used when the voltage is in the range of 0x0000 to 0x7FFF, and the other is used when the voltage is in the range of 0x8000 to 0xFFFF.
Moving average filter
We employed a moving average filter (Figure 4, below) in the FPGA in order to help the FPGA report highly accurate voltages and currents to the software. This filter is a 128 sample deep FIFO block that averages all of the samples. The filter operates on both voltage and current simultaneously, and it will operate on either calibrated or raw ADC values (but not at the same time). The filter is not used in the PID control loop. It is only used for reporting the values to the software for display to the user and computing energy.
Software can control the moving average filter through the register file interface. The features of the filter include the depth of the filter (max of 128 samples) and clearing the filter contents. A Filter Full bit is reported to the software to indicate that the output of the filter is valid. Software can also control whether the filter uses calibrated or uncalibrated data as its input. Using uncalibrated data is necessary during a board calibration.
When reading the average voltage, the average current at that instant is stored in a separate register. Software can then read this stored value to get a snapshot of what both the current and voltage were at the time of reading the voltage. The most recent current measurement is also made available through a separate register.
Figure 4: Moving Average Filter Block Diagram and State Machine Diagram (To view larger image, click here.)
Waveform tables
Waveform tables (Figure 5, below) are used to ramp the power setpoint over a period of time, creating a pulse edge, instead of instantaneously switching it on or off. There are two tables: one for the rising edge and one for the falling edge. The waveform table data scales the actual setpoint from 0 to 100 % (0x0000 to 0xFFFF). How this data is used is shown in the Waveform Control section below. The last data point in the waveform table is the steady state scale factor of the setpoint until the software triggers another pulse edge.
The benefit of the using the waveform tables is that the resultant waveform edge was much smoother when using the waveform table than without. The drawback is that the rise and fall times are naturally increased because the error on the early samples is much smaller than with a step input.
These tables proved to be useful once we got to the PID tuning stage of the project. Without the waveform table, non-idealities were present in the edges.
Having smooth, predictable edges was important in this system.
The content of the tables are written by software external to the FPGA design, through a system communication bus, at power-up. The software then only has to issue a single command to either call the rising edge or falling edge table.
The tables are just two blocks of FPGA internal RAM that are accessible by software. Each block of RAM has 16-bit wide data, 256 words deep. The PID loop frequency is 250 kHz, for a total edge length of approximately 1 ms.
Figure 5: Waveform Table Block Diagram (To view larger image, click here)
Waveform control
The waveform control block (Figure 6, below) is the interface between the Waveform Tables and core PID control block. When this block receives a start signal from the software, it starts to read the waveform tables.
Figure 6: Waveform Control Block Diagram(To view larger image, click here.)
It selects which waveform table to read, and then multiplies that normalized waveform data by the Waveform Amplitude from the register file to get a power setpoint for the PID control block.
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