Case study of PID control in an FPGA

Paul Schad and David Carney, Plexus

January 17, 2011

Paul Schad and David Carney, Plexus

PID state machine
The PID State Machine block of the FPGA (Figure 7 below) controls the flow of the entire digital PID loop. It controls each step in the pipeline from reading the raw voltage and current ADC registers through sending a value to the DAC. The current and voltage ADC interfaces send a ready signal to the state machine when they are ready to start another cycle.

The ADCs are enabled separately from the PID loop so that samples may be taken without trying to control the load. The ADCs will continue to take samples at 250 kSPS as long as they are enabled. The state machine will then clear the ready signals, and when both are activated the calibration starts. Once calibration is complete, the moving average filter will be triggered.

If the PID is enabled, the control loop will continue and compute a new DAC value. If the PID is disabled, the DAC will be set to a known value that is configurable by the software. When the PID is enabled again the math results registers will be cleared so that the PID loop will start from a clean state and not be influenced by any previous calculations.

The DAC communication will be started two clock cycles after the ADC conversion starts. This ensures that there will be no DAC activity during the ADC aperture time. The state machine diagram is below.

This state machine includes states for a pipelined implementation of the calculations. A simpler state machine with fewer pipeline states and wait states to wait for long combinational logic and embedded multiplier paths could be used to save register resources and potentially reduce total loop time. Using all of the intermediate pipeline registers does make it easier to debug the design in simulation.

 

Figure 7: PID State Machine Diagram(To view larger image, click here)

PID Control
The PID Control block compares the input power level (calculated from the calibrated voltage and current) to the setpoint power level and calculates an error. Based on this error, a DAC value is calculated that should result in a smaller error on the next iteration of the loop, assuming your parameters are tuned properly.

There are a number of ways to implement PID control in an FPGA. Our equation was based on the Type C equation described in the How to Select a PID Equation section. This is the same equation with some of the terms reordered to optimize the FPGA implementation [4]. The PID equation implemented in the FPGA is the following equation.

The PID parameter inputs for this equation are slightly different from the traditional KP, KI, and KD. This control algorithm uses parameters referred to as a0, a1, a2, and a3. They can be calculated from the traditional parameters and the PID control sample rate (Ts) of the loop. Those equations are the following:

The ax PID parameters are integer numbers between –(2-1) and 2-1. The power input and setpoint are integer numbers between 0x0000_0000 and 0xFFFF * 0xFFFF = 0xFFFE_0001. These numbers are in terms of ADC counts, not watts.

In order to deal with negative numbers, the sign of all numbers at each stage of the pipeline that could possibly be negative are tracked in a register separately from the unsigned math operations. The PID parameters could be negative so the signs of those numbers are saved into a register that is separate from the magnitude value.

Logic is then used on the magnitudes and signs of the operands to determine the appropriate math operation to perform and the sign of the result (i.e. a+b, a-b, or b-a for any two operands a and b). It was necessary to implement the math operations in this way instead of using signed numbers, because the embedded multipliers in the FPGA only work with unsigned numbers.

The PID Controller's(Figure 8, below) first calculation in a loop iteration is to find the present error, e(k). It subtracts the input power from the power setpoint. The input power and setpoint are both 32 bits wide so the 33rd bit of the result is then checked to see if the error is negative. If it is then its sign bit is set and the two’s complement is performed on the lower 32 bits, making the magnitude value positive again. e(k), y(k), y(k-1), and y(k-2) are then multiplied by the PID parameters.

Figure 8: PID Control Block Diagram (To view larger image, click here)

The sign bits of the multiplicands are XOR’d to get the sign bit of the product. Some logic will then compare the magnitudes and signs of each product (as well as that of u(k-1)) to determine the next appropriate operations (addition or subtraction and their order). The 14 MSBs (DAC data width) are passed to the output, excluding the sign and overflow bits.

All of the inputs into the PID Control block are integers. There are no decimal points in the math in this block. Each of the two Addition/Subtraction levels adds a carry bit to the paths so that at the output there are two carry bits.

These bits are not passed to the output because they only indicate an overflow. If either of these bits is set after the final addition/subtraction stage (see block diagram below), the output will be limited to its max (0x3FFF).

The feedback of this output back into the loop also needs to be limited to prevent windup [2]. If this prevention is not taken, it is possible for the controller to be continually accumulating error when the DAC is maxing out the load, and all of this accumulated error would need to be de-accumulated when the setpoint returns in the opposite direction.