Optimize data flow video apps by tightly coupling ARM-based CPUs to FPGA fabrics
Arm benefits
There are substantial benefits to the ARM processor and FPGA combination relative to other processor options. As mentioned earlier, the ARM architecture is very popular, and that popularity delivers what are at first glance surprising benefits beyond the fact that embedded design teams are familiar with the architecture and instruction set. Embedded applications can leverage a wealth of open source software as well as software developed for handsets such as the Android operating system and user interface.
It turns out that users of a specialized embedded system – such as a video-centric transportation system – greatly prefer a known user interface. Users are increasingly familiar with the touch-based handset interfaces and fingertip sweeps used for navigation. By leveraging Android, an embedded design team provides a popular user interface without having to develop custom user-interface software.
The iVeia ARM-based module supports Android in addition to applications developed for the Linux-based operating system. For example, a transportation application may include a GPS module. An ARM-based design running Android can provide the same GPS experience found on smartphones.
The ARM core has also been optimized for low power consumption through multiple generations of usage in handsets. The combination of an ARM processor and FPGA can offer lower power that translates to longer battery life in portable products.
Embedded design teams will have access to an even more powerful ARM processor and programmable logic implementation when Xilinx delivers the first Zynq-7000 devices next fall. The Zynq-7000 EPP family will integrate a dual-core ARM-Cortex-A9 based processor system with most advanced programmable logic into a single device. . The 28-nm devices will use Xilinx’s 7-series FPGA architecture that is the basis of the new Artix-7 and Kintex-7, products.
Unlike prior FPGA ICs that integrate hardened processor cores, the Zynq-7000 family of devices provide a comprehensive state-of-the-art microprocessor system that boots just as any other microprocessor IC. The products also have the on-chip programmable logic that, under control of the processing system, is configured after the processor boot-up sequence is completed.
Next-generation designs
A Zynq-7000-based embedded system will afford design teams another huge gain in system performance and a reduction in power consumption. Much of the performance advantage will come from even tighter integration between the processor core and the programmable logic .
The IC design will rely on the latest AMBA 4 (Advanced Microcontroller Bus Architecture) AXI (Advanced Extensible Interface) interconnect technology to interface the processor to functional blocks within the FPGA fabric.
AXI will offer three times wider buses that are four times faster than the interconnect used in the OMAP-based Atlas-I-LPe module, with a projected “orders of magnitude” lower power consumption for Zynq-7000-based designs over previous generation Virtex PowerPC designs.
iVeia has already demonstrated Android running on Xilinx’s Zynq-7000 Emulation Platform . While the effective clock rate of the processor emulation is low, the programmable logic operates at the specified frequency. iVeia has been able to demonstrate an Android application with live video via camera link interface. The Android application controls parameters such as image filter settings and other coefficient values used in object recognition and pattern matching used in imaging systems.
iVeia plans to have a module based on its Atlas form factor ready for shipment when Xilinx delivers the first Zynq-7000 EPPs. Indeed the company has already announced the Atlas-I-Z7e module.
The Atlas form factor measures 1.249x3.37 in. The Atlas-I-Z7e will utilize a Zynq-7020 IC that is based on the Artix-7 FPGA fabric that is optimized for low cost and low power. The processing system dual MP Cortex A9 ARM cores will operate up to 800 MHz.
Neon SIMD engines and single/double precision floating point units for each core are included as part of the processing system The design also will include 32 Kbytes of level 1 cache and 256 Kbytes of level 2 cache with 256Kbytes of on-chip memory accessible by the programmable logic via high speed interconnect switches.
The Z7020 device programmable logic includes 85,000 logic cells or about the equivalent of 1.3 million ASIC gates – offering significantly more processing resources than the Spartan-based predecessor, 220 programmable DSP slices and 560 kbytes of block RAM. The DSP resources more than make up for the lack of a DSP core in terms of processing real-time data streams. Indeed, independent DSP experts at BDTI have documented that FPGAs can offer 40x better performance than DSP-centric processors in real-time data-flow applications.
Embedded design teams can start development projects for the Atlas-I-Z7e now using the OMAP-based Atlas-I-LPe. The microprocessor cores in each are software compatible. Moreover, iVeia supplies what it calls the Velocity-EHF (Embedded Hybrid Framework) application portability layer for hybrid processor plus FPGA systems. The company claims that designs have been ported in a single day from modules based on a PowerPC-enabled Virtex FPGA to the OMAP-based Atlas-I-LPe. The port to the Zynq-7000-based module should be equally simple.
At the recent Embedded World conference in Nuremberg, Germany, iVeia showcased the Atlas-I-LPe production board and demonstrated full system interoperability using an emulation platform to prototype the Atlas-I-Z7e.
The system demonstrated was running Android 2.2 managing the image enhancement of a live video stream using custom AXI IP implemented in the programmable logic running on the emulation platform. You can watch a video of the Android application with live video manipulation on the EE Times web site .
Michael Fawcett is the Chief Technology Officer at iVeia (Annapolis, MD). You can contact him at michael.fawcett@iveia.com. Dan Isaacs is the Director of Processing Platform Marketing, Xilinx Inc. (San Jose, CA). You can contact him at dan.isaacs@xilinx.com.
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