Optimize data flow video apps by tightly coupling ARM-based CPUs to FPGA fabrics

Michael Fawcett, iVeia, with Dan Isaacs, Xilinx

May 10, 2011

Michael Fawcett, iVeia, with Dan Isaacs, XilinxMay 10, 2011

In this Product How-To design article, iVeia’s Michael Fawcett describes how combining an ARM-based TI OMAP CPU and Xilinx FPGAs can be used to design a system for handling rich data-flow video processing apps via the inherent parallel structure of an FPGA fabric.

Design teams have long used FPGAs in tandem with standard microprocessors both as a way to add peripheral functions and as a processing resource capable of operating on real-time data streams such as video. To maximize performance in such applications, designs must tightly couple the FPGA and microprocessor, instead of treating each as independent entities.

Today, off-the-shelf platforms tightly integrate the processor/FPGA combination. Development tools allow an embedded design team to optimally partition their design making tradeoffs between software or hardware implementations.

In the product design group at iVeia,we have been building systems that that closely link processors and FPGAs to create full featured advanced technology products for the video, communications, and handheld applications spaces. We are now working on a next-generation iVeia system that we think will be even more formidable using the new Xilinx Zynq-7000 Extensible Processing Platform, that marries dual ARM processors with the latest 28nm programmable logic on the same device (Figure 1 below).

Figure 1: Unlike previous chips that combine MPUs in an FPGA fabric, Xilinx’s new Zynq-7000 EPP family lets the ARM processor, rather than the programmable logic, run the show.  (To view larger image, click here)
Typical integration of FPGAs and CPUs
In a typical system, the microprocessor handles command and control and parts of an application such as audio codecs. The FPGA, meanwhile, can perform real-time tasks such as video codecs and image processing or performance-intensive communications algorithms in SDR (software defined radio) applications.

Of course design teams have had access to processors on FPGA ICs for some time. Xilinx and other FPGA vendors have offered design teams the ability to realize soft processor cores using the FPGA fabric. Moreover, some FPGAs have combined hardened processor cores as in the integration of PowerPC cores into the Xilinx Virtex family of FPGAs.

But both the soft processor approach and the aforementioned PowerPC-enabled FPGAs are FPGAs first and foremost. The FPGA fabric must be configured before a processor can boot, and the design process is centered on the FPGA development tool flow.

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