Taking a multicore DSP approach to medical ultrasound beamforming
This product how-to article describes how to use a Freescale DSP MSC8156 to produce diagnostically useful medical B-mode ultrasound imaging results, using no more than about 38% of the resources of the DSP, leaving enough room to also perform Doppler imaging.
A critical factor in the design of many medical ultrasound equipment designs is the effectiveness of the beamforming algorithms, a signal processing technique used in sensor arrays for directional signal transmission or reception. But until recently, the computational power needed to do such signal processing – at a reasonable cost and with the resolution needed for medical diagnostic purposes – was only possible with FPGAs and ASICS.
Now, however a new generation of dedicated digital signal processing architectures can bring a lot of processing power and highly parallel architectures to the problem at a much lower cost and at lower power.
This article describes how to use a Freescale DSP MSC8156 loaded with software libraries for B-Mode images that produce diagnostically useful medical ultrasound imaging results, using no more than about 38% of the resources of the DSP, leaving enough room to also fit Doppler Imaging modes.
In B-mode ultrasound, a linear array of transducers simultaneously scans a plane through the body that can be viewed as a two-dimensional image on screen, whereas in the Doppler mode, the ultrasound system makes use of the well-known Doppler effect to measure and visualize blood flow.
The ultrasound imaging problem
A classic architecture for ultrasound system, up to where the image is formed, can be visualized in Figure 1, below. Usually, in such architectures, dedicated hardware is used to perform signal processing tasks such as beam-forming. This approach lowers the flexibility of the system, making updates impractical (e.g. introducing new transducers that have different geometrical properties might imply changes that are more efficient to be done in software).
In this article, we will not go into details regarding transducers, pulsers, protection T/R switches and analog frontends; the interested reader can find information about these parts in the datasheets provided by different manufacturers.
Figure 1 – Classic architecture for an ultrasound system
To bring more flexibility into the system, we propose a software approach where all signal processing is done in software and FPGAs are employed as simple connectors. By using “off the shelf” hardware that is mature in terms of tools and “getting started” materials, a lower time to market can be expected (Figure 2 below ).
Figure 2 – Proposed architecture with Beamforming done on DSP
Today solutions for 32 channels, based on FPGAs, can be divided into categories as in Table 1 below. While for small and medium large FPGAs dynamic focusing and apodization is hardly achievable on high end FPGAs almost any feature is available, leaving a gap in image quality for low and mid – end devices. Due to the fact that the delay and apodization coefficients can be pre-calculated and stored into memory, a DSP approach can prove to be efficient in implementing beamforming, as long as the processing power is sufficient.
Table 1 – FPGAs, DSPs capabilities
Applying the MSC8156 to the problem
In terms of costs, DSPs have a clear advantage over high end FPGAs and are suitable for low and mid end devices. The following shows how dynamic focusing and dynamic apodization, features that are usually in expensive FPGAs, can be implemented also on lower cost DSPs (Figure 3 below).
Figure 3 – Features supported vs. price
The DSP selected for the study is MSC8156, a six core device from Freescale Semiconductor that is widely used in baseband, voice and video applications.
To meet the high-data-rate and demanding computational requirements of medical ultrasound imaging application, DSP architectures have to be analyzed based of five critical criteria: parallelism, memory bandwidth, IO bandwidth, instruction set and hardware accelerators.
Freescale’s MSC8156 serves these applications with a high parallel architecture that has six cores running at 1GHz, each core having four Data Arithmetic-Logic Units, where up to four arithmetic and logic operations can be executed in a single clock cycle, and two Address Generation Units, where usually integer operations and address generation is performed (Figure 4 below).
Figure 4 – High level block diagram of MSC8156 (To view larger image, click here)
In terms of memory, MSC8156 features an on SoC M3 memory of 1MB with a theoretical speed of about 8GBps and the capability to connect two DDR3 memories of up to 1GB each with a theoretical bandwidth of about 12GBps.
Since we are dealing with high data rates, Serial Rapid IO is elected as the interface of choice. MSC8156 has two Rapid IO ports for that the measured speed for one port and one direction can be up to 9.11Gbps.
Beamforming algorithms, such as delay and sum, make use of interpolation operations implementable by packed instructions like:
For Doppler imaging modes such as Spectral Doppler, the FFT/DFT accelerator MAPLE-B might be of interest. While MAPLE is executing FFTs the cores are free to execute modules for other imaging modes.