Guide to VHDL for embedded software developers: Part 3 - ALU logic & FSMs

Peter Wilson

July 25, 2011

Peter Wilson

Clearly we could define more functions, and this would require more bits for the select function (S), but this limited set of functions demonstrates the principle involved. We can define a modified entity as shown below:

Library ieee;
Use ieee.std_logic_1164.all;
Entity alu_logic is
    Generic (
          N : natural:= 16
    );
    Port (
         A : in std_logic_vector((n-1) downto 0);
         B : in std_logic_vector((n-1) downto 0);
         S : in std_logic_vector(1 downto 0);
         Q : out std_logic_vector((n-1) downto 0)
    );
End entity alu_logic;

Now, depending on the value of the input word (S), the appropriate logic function can be selected. We can use the case statement introduced in the VHDL primer chapter of this book to define each state of S and which function will be carried out in a very compact form of VHDL:

Architecture basic of alu_logic is
Begin
    Case S is
        When “00” => Q <= NOT A;
        When “01” => Q <= A AND B;
        When “10” => Q <= A OR B;
        When “11” => Q <= A XOR B;
    End case;
End architecture basic;

Clearly this is an efficient and compact method of defining the combinatorial logic for each state of the control word (S), but great care must be taken to assign values for every combination to avoid inadvertent latches being introduced into the logic when synthesised.

1-bit adder
The arithmetic ‘hear t’ of an ALU is the addition function – the Adder. This starts form a simple 1 bit adder and is then extended to multiple bits, to whatever sized of addition function is required in the ALU. The basic design of a 1-bit adder is to take two logic inputs (a & b) and produce a sum and carry output according to the truth table in Table 4 below:

Table 4

This can be implemented using simple logic with a 2 input AND gate for the carry, and a 2 input XOR gate for the sum function as shown in Figure 1 below.

Figure 1. Simple 1 bit adder
This function has a carry-out (carry), but no carry-in, so to extend this to multiple bit addition, we need to implement a carryin function (cin) and a carry-out (cout) as shown in Table 5 below and with an equivalent logic function as shown in Figure 2 below.

Figure 2. A 1-Bit Adder with Carry-in and Carry-out

Table 5
As shown above, this can be implemented using standard VHDL logic functions with bit inputs and outputs as follows.

First define the entity with the input and output por ts defined using bit types:

entity full_adder is
port (sum, co : out bit;
a, b, ci : in bit);
end entity full_adder;

Then the architecture can use the standard built-in logic functions in a ‘dataflow’ type of model, where logic equations are used to define the behaviour, without any delays implemented in the model.

architecture dataflow of full_adder is
begin
   sum <= a xor b xor ci;
   co <= (a and b) or
         (a and ci) or
         (b and ci);
end architecture dataflow;

This model is now a simple building block that we can use to create multiple bit adders structurally by linking a number of these models together.