Designing with core-based high-density FPGAs

Robert S. Grimes

July 27, 2011

Robert S. Grimes

Hardware design
The approach we took during the design of this system was to first partition the required functionality into two separate processing elements because the overall system design divided the system into a laser assembly and a supporting electronics rack (shown in Figure 1). The laser assembly contains the four laser resonators, optics, Q-switches, and the high-speed photodiode diagnostic sensors, and had to conform to strict physical interfaces.


Click on image to enlarge.
Because of several high-level decisions, the design of the laser assembly was further partitioned into two identical halves, each implementing two of the four lasers; therefore, the laser electronics also consists of two identical assemblies. The supporting rack fills a standard 19-inch electronics rack, and contains power converters, Q-switch drivers, eight high-power laser pump diodes and their drivers, host interfaces, and the master processor.

So, due to our high-level requirements (the laser assembly and support rack approach) and the resulting system design, the electronics design evolved into a multiprocessor solution, with three processors networked together to satisfy the functionality demanded.

To keep the development effort manageable, the three processor assemblies utilize a common "digital board," each augmented with different analog boards; of course, the two laser processors used the same analog board design.

Here is the first instance where the flexibility of the Virtex-4FX devices paid real benefits; because the two analog board designs required different mixes of analog-to-digital (A/D) and digital-to-analog (D/A) converters, as well as various other digital I/O interfaces, it would have been difficult to meet both sets of I/O without significant waste.

However, by putting the actual interface circuits (such as photodiode circuitry, A/D converters, serial line drivers) onto the custom analog board, the interconnection between the two boards consists largely of direct FPGA I/O connections; hence, a different configuration, with the appropriate IP peripherals, allowed the same processor board to implement different functionality.

Now that the high-level system architectural decisions had been made, it was time to detail the designs of each of the processor subsystems. The first step was to separate the data acquisition and, where applicable, real-time analysis functions into high-rate and low-rate categories. The high-rate analyses were limited to relatively simple, high-speed algorithms that are performed on input data stream by dedicated FPGA logic. Lower-rate, more complex analyses performed on buffered data, assisted by the stream processing.