Basics of core-based FPGA design: Part 2 – System design considerations

R.C. Cofer and Ben Harding

August 21, 2011

R.C. Cofer and Ben Harding

Bus Implementation Performance Improvement Factors
1) Increased operational speed
2) Use of wider bus widths
3) Decoupling of data and address transfers 4)Use of burst sequential access
5) Write buffer implementation
6) Support for both synchronous/asynchronous interfaces
7) Implementation of endianness (TCP/IP uses big endian)
8) Use of error detection/correction to maintain bus integrity
9) Use of the direct memory access (DMA) controller

Two common architectural bus implementations are Harvard and von Neumann bus architectures. The Harvard bus architecture is a two-bus implementation, supporting instruction and data access simultaneously. A majority of modern processors implement Harvard bus architecture interfaces.

An enhanced version of the Harvard architecture, called the modified Harvard architecture, includes two data buses to increase bus bandwidth. This architectural bus implementation is commonly seen on modern digital signal processors. The von Neumann bus architecture uses a single bus to access data and instructions.

One of the benefits of this less-complex bus architecture is that it requires fewer pins. Von Neumann is typically the common bus implementation for external or off-chip devices. For processor implementation within an FPGA, the trade-off between the two bus architectures is heavily dependent upon the number of FPGA I/O pins that must be used to implement the selected bus.

A disadvantage of von Neumann architecture is that the single data path may cause bottlenecks, thus producing degraded performance when compared with a Harvard implementation. An enhanced version of the von Neumann implementation is the modified von Neumann.

This implementation allows faster transaction times by running the bus clock faster than the processor core. However, due to the speeds of modern processors, this approach is not as practical.

Efficient interrupt implementation is an important factor in deterministic real-time embedded systems. The implementation of an interrupt controller provides a low latency mechanism for signaling the processor core when a device needs attention.

The interrupt controller provides the prioritization of processor peripheral events for devices attached to the processor core. The interrupt controller will typically be provided by the processor vendor as IP. The use of shadow registers can enhance fast context switching during interrupts. Interrupt software implementations should be fast and efficient. Lengthy computational processing should be limited to application code.

The MMU block provides a translation mechanism between the logical program data space, and the physical memory space. The MMU may be used to extend the range of accessible external memory. MMU implementation is usually accomplished by separating the data and instruction memory regions. Typically, the software implementation complexity will be increased when an MMU is used. The implementation of an MMU within a processor may have a significant effect on the processors real-time performance.

A final architectural consideration is the data-path for the software program. A processor is based on an efficient sequential instruction flow. Instruction flow interruptions and disturbances will impact performance. Floorplanning can be used to implement an optimized processor implementation data-path.

To read Part 1 go to: FPGA core types and trade-offs
Next in Part 3:  Processor, peripheral and software options

Used with permission from Newnes, a division of Elsevier. Copyright 2006, from “Rapid System Prototyping with FPGAs,” by R.C. Cofer and Ben Harding. For more information about this title and other similar books, please visit www.elsevierdirect.com.

RC Cofer has almost 25 years of embedded design experience, including real time DSP algorithm development, high speed hardware, ASIC and FPGA and project focus. His technical focus is on rapid system development of high speed DSP and FPGA based designs. He holds an MSEE from the University of Florida anda BSEE from Florida Tech.

Ben Harding has a BSEE from the University of Alabama, with post-graduate studies in DSP, control theory, parallel processing and robotics. He has almost 20 years of experience in embedded systems design involving DSPs, network processors and programmable logic.