Basics of core-based FPGA design: Part 3 – Picking the right core options

R.C. Cofer and Ben Harding

August 21, 2011

R.C. Cofer and Ben Harding

Hardware Implementation Factors
During the hardware design effort, a few key hardware factors should be taken into consideration. Hardware implementation factors associated with FPGA embedded processor design include device-level, board-level, design optimization, embedded processor setup, and IP use.

All of these design factors are interrelated. Important items affecting the embedded processor design optimization process include FPGA device design margin, FPGA board orientation, data flow through the FPGA, informed pin assignment, utilization of unused pins, access to internal FPGA signals, and clocking. The following list summarizes these embedded processor design factors.

Key Hardware Design Factors 

1) Tool selection
2) Design margin
3) Device selection
4) Design optimization
5) Data flow and FPGA orientation
6) Debug hooks
7) System clocking
8) Bus interconnection and management strategy
9) Device mapping
10) IP usage

Some of the factors affecting tool selection are traditional FPGA design implementation capabilities, IP integration, target FPGA selection, and interoperability of traditional FPGA design tools and processor implementation tools.

An important tool consideration is the method and flow used to build the embedded processor. Typically the design tool flow implementation options range from manual to highly automated. The manual flow allows a high level of control over the system implementation, but at the cost of time.

The automated flow can implement a broad range of design functionality. Complex designs are often implemented using a combination of the two flows. The first design pass can be implemented with the assistance of automated wizards, with more detailed modification and enhancements being implemented manually.

Software Implementation Factors
Software development for an FPGA embedded processor is very similar to the flow and process of software development for a conventional discrete processor. As with any other design effort, tools play a key role in a successful development effort. At the core of the software tool chain is the integrated development environment (IDE).

This tool suite brings together an editor, optimizing compiler, incremental linker, make utility, simulator and non-intrusive debugger. A good example of a popular IDE is the Eclipse IDE. Popular compiler and debugger tools are gcc and gdb.

Even with the best tools, the software design implementation can increase in complexity to a point where additional levels of software abstraction are required. With the increased software abstraction levels, the embedded system must still be able to exhibit real-time response to the events it handles.

A real-time operating system (RTOS) can be used to implement a level of abstraction while also supporting real-time event handling. In order to meet critical timing requirements, the selected embedded operating system must have a level of determinism sufficient to provide an acceptable real-time response as it relates to the system in question. The two categories for determinism are hard and soft. Soft determinism causes the largest amount of event timing jitter (timing uncertainty).

A good RTOS solution must provide real-time deterministic performance while also connecting the lower-level software to the hardware. The package that provides this lower-level connection is called the board support package (BSP). A BSP includes the boot code for the initialization of the processor, low-level drivers and interrupt service routines for peripherals and related system hardware.

A good RTOS will also include important middleware components including, but not limited to, TCP/IP stack, web server, USB stack, encryption software, and other popular devices.

There are many items to consider during the selection of an RTOS. Some of the most important considerations are the API set, tasking model, kernel robustness, interrupt response and footprint.

Any processor core under consideration will typically have a list of supported or certified operating systems that have been verified.

A final design factor relating to RTOS implementation that can influence a project’s schedule is the integration between the selected RTOS and IDE tool set. Tight coupling between the RTOS and the implementation tool set can improve efficiency by providing additional debugging capability.

One of these capabilities is task profiling, which is used to ensure that the software implemented follows the defined priority and resource management schemes. Considerations important in the selection and implementation of an RTOS is presented in the following list.

RTOS Selection Factors 

1) Determinism
– Is the kernel hard or soft?
2) Defines amount of timing uncertainty
3) Scheduling effects robustness
– Priority-based
– Preemption versus nonpreemption
5) Preemptive is used in real-time systems
6) Use a standardized API set
– Wrappers assist where no API standard exists
7) Understand synchronization and communication approaches
– Avoid deadlock
– Task communications promotes better code readability and reuse at the cost of more memory utilization
8) Use task to partition
– Promotes compartmentalization for code reusability
9) Understand memory usage model
– Task stack size
– Avoid stack overflow issues 10)Use the best licensing model for controlling cost/effort
– Is “ free” really free?
– Similar for hardware IP

Next in Part 4: Implementing a design
To read Part 1, go to Core types and trade-offs
To read Part 2, go to System Design Considerations

Used with permission from Newnes, a division of Elsevier. Copyright 2006, from “Rapid System Prototyping with FPGAs,” by R.C. Cofer and Ben Harding. For more information about this title and other similar books, please visit www.elsevierdirect.com.

RC Cofer has almost 25 years of embedded design experience, including real time DSP algorithm development, high speed hardware, ASIC and FPGA and project focus. His technical focus is on rapid system development of high speed DSP and FPGA based designs. He holds an MSEE from the University of Florida anda BSEE from Florida Tech.

Ben Harding has a BSEE from the University of Alabama, with post-graduate studies in DSP, control theory, parallel processing and robotics. He has almost 20 years of experience in embedded systems design involving DSPs, network processors and programmable logic.