Basics of core-based FPGA design: Part 4 – Implementing a design

R.C. Cofer and Ben Harding

August 22, 2011

R.C. Cofer and Ben Harding

The assignment of peripheral devices to the OBP and PLB buses is an important design step. The PLB bus assignments include the DDR memory controller, the Flash memory controller, the PCI bus controller, and the tri-mode MAC. The OPB bus assignments include the I2C controller, the SPI controller, the UART block and the GPIO interface pins accessing external LEDs and switches.

Additional devices added to the OPB include a system timer and an interrupt controller. The assignment of these blocks to the appropriate buses has a huge potential influence on the implemented processor’s efficiency. For example, connecting the PCI bus controller to the OPB bus would significantly degrade performance limiting design functionality.

Additional information can be found in Xilinx application note XAPP709 DDR SDRAM Controller Using Virtex-4 Devices, and XAPP701 Memory Interfaces Data Capture Using Direct Clocking Technique. Additional Ethernet interface information can be found in Xilinx application note XAPP443

Ethernet Cores Hardware Demonstration Platform
This design requires performance acceleration. Internal cache functionality will be enabled. The design also takes advantage of the 405 PowerPC core processor auxiliary processing unit (APU) interface to communicate efficiently with the DSP coprocessor functionality implemented within the FPGA.

The APU supports a high-bandwidth interface between the FPGA logic fabric and the pipeline of the 405 core. Details of an APU implementation may be found in Xilinx’s application note XAPP 717 Accelerated System Performance with the APU Controller and XtremeDSP Slices. Additional information may be found in Xilinx’s PowerPC Instruction Set Extension Guide.

The design also implements an interrupt controller. The interrupt controller is used to add additional interrupt lines. The PowerPC core natively supports two interrupt pins. These two interrupt inputs support critical and noncritical interrupts, respectively. Design details are presented in Xilinx’s application note XAPP778 Using and Creating Interrupt-Based Systems.

The main goal in using these processor features is to reduce the number of external memory accesses and decrease peripheral event response latency. Additionally, the DMA controller was used for the Ethernet device to increase data throughput and to off-load the processor core. Additional information on performance enhancement can be found in Xilinx’s ETP-367 paper “FPGA Embedded Processors: Revealing True System Performance.”

Many different software design implementation approaches can be taken to implement a set of fixed-functional requirements. The following paragraphs presents a potential viable set of software design decisions and factors. These are, of course, not the only potential solutions for implementing the required functionality; however, they should serve as a high-level design approach example. Figure 14.5 below illustrates the interrelationship between the hardware and software development flows.

Figure 14.5. Co-design Hardware and software tool interaction
The operating system selected for this example implementation is uCLinux. It is a good choice because it provides source code access, a TCP/IP stack and is a popular OS solution. Since uCLinux does not require an MMU, the MMU functionality of the 405 core is disabled. Software debugging may be streamlined by taking advantage of network file system (NFS) capability and gdbserver.

NFS allows a developer to export a working directory to a remote uClinux platform. This allows developers to compile code on their desktop development platform and then run the code remotely on the target system. The gdbserver program is the target server that provides connection to the development system gdbdebugger tool.

Another important design consideration is the order of code execution. As an example, it is common for a peripheral to require a specific register access order during the device’s initialization phase. It is possible for the PowerPC core to implement nonsequential instruction execution. A PowerPC instruction that can prevent out-of-sequence instruction execution is the enforced in-order execution of IO (EIEIO) command.