Using configurable processors as alternatives to FPGAs

Warren Miller, Independent Consultant

July 08, 2013

Warren Miller, Independent ConsultantJuly 08, 2013

Configurable processors can implement many compute oriented functions FPGAs can address but with some distinct advantages. I talked to Bob Beachler, vice president of marketing, operations, and system design at Stretch Inc. about their innovative approach to software configurability.

This approach operates at a higher level than traditional FPGA methodologies and allows pure software engineers the capability to create custom solutions without the need to get into the details of the hardware.

Customize your processor, not your logic gates
Bob started out our discussion by stating that Stretch is a microprocessor company that puts programmable fabric inside the processor. This may seem like a subtle difference between the host of FPGA companies that are now putting processors on FPGAs, but it is an important one.

The design methodology Stretch employs targets high-level C/C++ code and not gates like traditional FPGA-based implementations. In the Stretch model the C/C++ code runs on the processor just link any other processor-based implementation. Stretch uses an extensible processor architecture however that provides a variety of software acceleration options to the programmer (or the optimizing compiler).

As illustrated in Figure 1 below, the Stretch S6 device has a variety of high-speed interfaces optimized for supporting audio, video, and wireless applications including a DDR2 controller, 10/100/1000 Ethernet MAC, PCIe, I2C, and support for a wide variety of video and audio interface standards.

The Software configurable processor (SCP) implements the computing oriented functions. An Xtensa LX Very Long Instruction Word (VLIW) processor core can run standard C/C++ code similar to traditional processors but it also offers the ability to add hardware acceleration via customized instructions that can "hook" directly into the application C/C++ code.

Figure 1: SerDes Implementation Block Diagram- Xilinx Series 7 FPGAs.
Two methods are available to target hardware acceleration functions: Pre-defined and optimized acceleration functions (the Programmable Accelerator) and the Instruction Set Extension Fabric (ISEF).

The Programmable Accelerator functions are defined for the market segment a Stretch device family is optimized for -- in the case of the S6000 Family these are audio, video and wireless markets.

Figure 2: ISEF connection to the other processor blocks
Dedicated functions include Encryption, Entropy Encoding, Motion Estimation, and a HIFI 2 audio engine. The other implementation approach for hardware acceleration is to use the ISEF block within the Xtensa LX processor core. The ISEF connection to the other processor blocks is shown in the Figure 2 above.

To read more, go to “Using the ISEF connection.”

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